Patents by Inventor Wei Lin

Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Publication number: 20240147646
    Abstract: A portable data accessing device and more particularly the use of multi-port interfaces on a data accessing device disclosed. The multi-port data accessing device includes an inner body, one or a plurality of moving-caps, one or a plurality of grips, a pump-action and one or a plurality of locking/releasing mechanisms.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Yi-Ting Lin, Hsien-Chih Chang, Chang-Hsing Lin, Hao-Yin Lo, Ben Wei Chen
  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
  • Publication number: 20240144719
    Abstract: A computing device obtains an image depicting an image of a user's face. The computing device identifies one or more regions in the image depicting skin of the user and generates a skin mask. A skin tone of the user's face is predicted and the skin mask is populated according to the predicted skin tone. The computing device defines feature points corresponding to facial features on the user's face and extracts pre-defined facial patterns matching facial features depicted in the image. The extracted pre-defined facial patterns are inserted into the skin mask based on the feature points and a hair mask identifying one or more regions depicting hair of the user is generated. The computing device extracts a hair region depicted in the image of the user based on the hair mask and inserts the hair region on top of the skin mask to generate a face chart.
    Type: Application
    Filed: September 18, 2023
    Publication date: May 2, 2024
    Inventors: Guo-Wei LI, Kuo-Sheng LIN
  • Publication number: 20240145733
    Abstract: Provided a catalyst for OER/ORR, including: an alloy oxide core having a particle size of 30 to 40 nm; and a carbon layer having a thickness of 1 to 7 nm, which is coated on a surface of the alloy oxide core, wherein the alloy oxide is a ternary to quinary alloy oxide, and the metal element contained in the alloy oxide is a transition metal element. Also provided is a method for preparing catalysts for OER/ORR by an electrospinning process. Accordingly, the prepared catalyst has excellent OER and ORR characteristics.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 2, 2024
    Inventors: Jyh-Ming TING, Kai-Wei LIN
  • Publication number: 20240145554
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Publication number: 20240144426
    Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.
    Type: Application
    Filed: April 20, 2023
    Publication date: May 2, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Shang-Yen Lin, Yi-Ting Bao, HAO-RAN WANG, Chia-Wei Yu
  • Publication number: 20240143649
    Abstract: A method for processing media content includes: receiving a selection on a media segment in a media content, where the media content comprises at least two media segments; determining a target media segment based on the selection; and receiving a request for processing the target media segment, in response to a triggering on the target media segment; wherein in response to the request including a request for re-capturing processing, the method further includes: re-capturing a plurality of media segments; and replacing the target media segment with the at least one media segment of the plurality of media segments.
    Type: Application
    Filed: December 19, 2023
    Publication date: May 2, 2024
    Inventors: Zhaoqin LIN, Wei Jiang, Qifan Zheng, Chen Shen
  • Publication number: 20240144550
    Abstract: A computing device obtains an image depicting an image of a user's face. The computing device identifies facial features in the user's face in the image and extracts characteristics of the facial features in the user's face in the image. The computing device predicts a skin tone of the user's face depicted in the image and generates a face chart based on the facial feature characteristics. The computing device adjusts a color of a facial region in the face chart according to the predicted skin tone and obtains lighting characteristics of the image of the user's face. The computing device adjusts one or more colors in the face chart based on the lighting characteristics of the image of the user's face.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 2, 2024
    Inventors: Kuo-Sheng LIN, Guo-Wei LI
  • Publication number: 20240145600
    Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih WEN, Yi-Lin YANG, Hai-Ching CHEN
  • Publication number: 20240144428
    Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.
    Type: Application
    Filed: June 28, 2023
    Publication date: May 2, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Tien-Hung Lin, Chia-Wei Yu, Yi-Ting Bao
  • Publication number: 20240144305
    Abstract: A method for allocating perishable products based on machine learning, includes using a sales estimation model to evaluate estimated sales of a plurality of perishable products in a predetermined period, using a rating model to calculate a predetermined rate of the plurality of perishable products in the predetermined period according to the estimated sales, using an allocation model to adjust an allocation ratio of the plurality of perishable products in a plurality of marketing channels according to the estimated sales and the predetermined rate if a current rate is lower than the predetermined rate, and determining the numbers of perishable products allocated to the plurality of marketing channels according to the allocation ratio.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: DUN-QIAN Intelligent Technology Co., Ltd.
    Inventors: Yen-Chu Chen, Ling-Jung Lin, Shao-Chen Liu, Hsuan-Wei Chen, Shuh-Shian Tsai
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Publication number: 20240145319
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Publication number: 20240142727
    Abstract: An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Sin-Yuan MU, Chia-Sheng CHENG
  • Publication number: 20240144585
    Abstract: A computing device obtains an image depicting a face of a user. The computing device identifies facial features in the image and extracts characteristics of the facial features in the image. The computing device generates a two-dimensional (2D) face chart based on the facial feature characteristics. The computing device predicts a skin tone of the user's face depicted in the image of the user and changes color in a color map of a predefined three-dimensional (3D) model based on the predicted skin tone. The computing device selects a predefined environment map based on characteristics in the image depicting the face of the user and generates a target face image based on the predefined 3D model.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: I-Ting SHEN, Yi-Wei LIN, Pei-Wen HUANG
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240145475
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: SHIH-WEI PENG, TE-HSIN CHIU, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Publication number: 20240145433
    Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 2, 2024
    Inventors: Po-Yao Lin, Chia-Hsiang Lin, Chien-Sheng Chen, Kathy Wei Yan