Patents by Inventor Wei-Long Wang
Wei-Long Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10055535Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: GrantFiled: September 27, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Piyush Pathak, Robert C. Pack, Wei-Long Wang, Karthik Krishnamoorthy, Fadi S. Batarseh, Uwe Paul Schroeder, Sriram Madhavan
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Publication number: 20180089357Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Piyush PATHAK, Robert C. PACK, Wei-Long WANG, Karthik KRISHNAMOORTHY, Fadi S. BATARSEH, Uwe Paul SCHROEDER, Sriram MADHAVAN
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Patent number: 9305800Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.Type: GrantFiled: February 20, 2014Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Tamer Coskun, Wei-Long Wang, Azat Latypov, Yi Zou
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Patent number: 9286434Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.Type: GrantFiled: May 23, 2014Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Yi Zou, Wei-Long Wang, Azat Latypov, Tamer Coskun
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Patent number: 9208275Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.Type: GrantFiled: February 25, 2014Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Wei-Long Wang, Azat Latypov, Yi Zou, Tamer Coskun
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Publication number: 20150339429Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Yi Zou, Wei-Long Wang, Azat Latypov, Tamer Coskun
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Patent number: 9122160Abstract: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.Type: GrantFiled: March 15, 2013Date of Patent: September 1, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Gek Soon Chua, Yi Zou, Wei-Long Wang, Byoung Il Choi
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Publication number: 20150242555Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Wei-Long Wang, Azat Latypov, Yi Zou, Tamer Coskun
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Publication number: 20150235839Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Tamer Coskun, Wei-Long Wang, Azat Latypov, Yi Zou
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Patent number: 8943445Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.Type: GrantFiled: December 12, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen
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Publication number: 20140282299Abstract: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Gek Soon CHUA, Yi Zou, Wei-Long Wang, Byoung IL Choi
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Publication number: 20140101623Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.Type: ApplicationFiled: December 12, 2013Publication date: April 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pi-Tsung CHEN, Ming-Hui CHIH, Ken-Hsien HSIEH, Wei-Long WANG, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU, Wen-Ju YANG, Gwan Sin CHANG, Yung-Sung YEN
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Patent number: 8631379Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.Type: GrantFiled: February 9, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen
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Patent number: 8381153Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: GrantFiled: September 17, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J. H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Patent number: 8378319Abstract: A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam.Type: GrantFiled: March 22, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Faruk Krecinic, Shy-Jay Lin, Jeng-Horng Chen, Shih-Ming Chang, Tuane Ying Fang, Wei-Long Wang, Chien-Hsun Chen
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Publication number: 20120072874Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J.H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Publication number: 20110226970Abstract: A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Faruk Krecinic, Shy-Jay Lin, Jeng-Horng Chen, Shih-Ming Chang, Tuane Ying Fang, Wei-Long Wang, Chien-Hsun Chen
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Publication number: 20110197168Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen