Abstract: A computer-implement method for exchanging data between a blockchain system and a non-blockchain system is provided. The method includes: adding, by endorser nodes, periodically a plurality of status information of the endorser nodes to a smart contract of a blockchain ledger; receiving, by a first peer node, a transaction from an application; sending, by the first peer node, the received transaction to all endorser nodes; processing, by the endorser nodes, the transaction via the smart contract to obtain a plurality of endorsements; electing, by the endorser nodes, one of the endorser nodes as a target endorser node according to the status information of the endorser nodes; and transferring, by the target endorser node, the endorsed transaction to the non-blockchain system via an API corresponding to the non-blockchain system.

Abstract: A computer-implement method for exchanging data between a blockchain system and a non-blockchain system is provided. The method includes: adding, by endorser nodes, periodically a plurality of status information of the endorser nodes to a smart contract of a blockchain ledger; receiving, by a first peer node, a transaction from an application; sending, by the first peer node, the received transaction to all endorser nodes; processing, by the endorser nodes, the transaction via the smart contract to obtain a plurality of endorsements; electing, by the endorser nodes, one of the endorser nodes as a target endorser node according to the status information of the endorser nodes; and transferring, by the target endorser node, the endorsed transaction to the non-blockchain system via an API corresponding to the non-blockchain system.

Abstract: A hardware accelerator for accelerating the zero knowledge succinct non-interactive argument of knowledge (zk-SNARK) protocol by reducing the computation time of the cryptographic verification is disclosed. The accelerator includes a zk-SNARK engine having one or more processing units running in parallel. The processing unit can include one or more multiply-accumulate operation (MAC) units, one or more fast Fourier transform (FFT) units; and one or more elliptic curve processor (ECP) units. The one or more ECP units are configured to reduce a bit-length of a scalar di in an ECP algorithm used for generating a proof, thereby the cryptographic verification requires less computation power.

Abstract: A hardware accelerator for accelerating the zk-SNARK protocol by reducing the computation time of the cryptographic verification is disclosed. The accelerator includes a zk-SNARK engine having one or more processing units running in parallel. The processing unit can include one or more multiply-accumulate operation (MAC) units, one or more fast Fourier transform (FFT) units; and one or more elliptic curve processor (ECP) units. The one or more ECP units are configured to reduce a bit-length of a scalar cl, in an ECP algorithm used for generating a proof, thereby the cryptographic verification requires less computation power.

Abstract: A Power-Line Communication (PLC) receiver has a filter, a time domain processor, a frequency-domain processor, and a forward-error-correction decoder. A narrow-band frequency detector attached to the frequency-domain processor examines the frequency-domain signal for a highest-power sub-carrier frequency. This highest power is compared to an average power of all other sub-carriers and a narrow-band interferer is detected when the highest power is significantly above the average. When the interferer is detected N times in a time period, a control layer adds this sub-carrier frequency to a removed list and recalculates filter coefficients to add a notch filter at the frequencies of the removed list. Updated filter coefficients are loaded into the filter to implement notch filters. When the current power of a sub-carrier signal on the removed list falls significantly below the average power, the sub-carrier is deleted from the removed list and coefficients recalculated to remove the notch filter.

Abstract: A Sampling Frequency Offset (SFO) tracking and estimation circuit performs SFO compensation on incoming data. A SFO acquisition module makes an initial coarse estimate using a Network Time Base (NTB) from the Media-Access-Controller (MAC) layer, or from the physical layer using adjacent synchronization symbols. A preamble channel estimator compares a frequency-domain preamble symbol to a reference symbol to generate a first channel estimate. As additional symbols are received, converted to the frequency domain, demodulated, and error corrected, the resulting data are re-error-encoded and compared to the same symbol stored before error correction and demodulation to generate a decision feedback channel estimate. The conjugate of the decision feedback channel estimate is multiplied by the last channel estimate to generate a new SFO estimate that is scaled by a filter constant and used to adjust SFO compensation. Each symbol generates a new estimate without using pilots.

Abstract: A Power-Line Communication (PLC) receiver has a filter, a time domain processor, a frequency-domain processor, and a forward-error-correction decoder. A narrow-band frequency detector attached to the frequency-domain processor examines the frequency-domain signal for a highest-power sub-carrier frequency. This highest power is compared to an average power of all other sub-carriers and a narrow-band interferer is detected when the highest power is significantly above the average. When the interferer is detected N times in a time period, a control layer adds this sub-carrier frequency to a removed list and recalculates filter coefficients to add a notch filter at the frequencies of the removed list. Updated filter coefficients are loaded into the filter to implement notch filters. When the current power of a sub-carrier signal on the removed list falls significantly below the average power, the sub-carrier is deleted from the removed list and coefficients recalculated to remove the notch filter.

Abstract: Multi view images are generated with reduced flickering. A first depth map is generated from stereo images by stereo-matching. When stereo-matching is poor or varies too much from frame to frame, disparity fallback selects a second depth map that is generated from a single view without stereo-matching, preventing stereo-matching errors from producing visible artifacts or flickering. Flat or textureless regions can use the second depth map, while regions with good stereo-matching use the first depth map. Depth maps are generated with a one-frame delay and buffered. Low-cost temporal coherence reduces costs used for stereo-matching when the pixel location selected as the lowest-cost disparity is within a distance threshold of the same pixel in a last frame. Hybrid view synthesis uses forward mapping for smaller numbers of views, and backward mapping from the forward-mapping results for larger numbers of views. Rotated masks are generated on-the-fly for backward mapping.

Abstract: Multi view images are generated with reduced flickering. A first depth map is generated from stereo images by stereo-matching. When stereo-matching is poor or varies too much from frame to frame, disparity fallback selects a second depth map that is generated from a single view without stereo-matching, preventing stereo-matching errors from producing visible artifacts or flickering. Flat or textureless regions can use the second depth map, while regions with good stereo-matching use the first depth map. Depth maps are generated with a one-frame delay and buffered. Low-cost temporal coherence reduces costs used for stereo-matching when the pixel location selected as the lowest-cost disparity is within a distance threshold of the same pixel in a last frame. Hybrid view synthesis uses forward mapping for smaller numbers of views, and backward mapping from the forward-mapping results for larger numbers of views. Rotated masks are generated on-the-fly for backward mapping.

Abstract: A system comprising a central processing unit (102) for use in executing RISC instructions and a hardware unit (100) associated with the central processing unit (102), is disclosed. The hardware unit (100) is configured for translating stack-based instructions into RISC instructions for execution by the central processing unit (102). The translation is performed using a programmable lookup table.