Patents by Inventor Wei-Lun K. Jen
Wei-Lun K. Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317592Abstract: In one embodiment, a package substrate includes a substrate core, buildup layers, and one or more conductive traces. The substrate core includes at least one dielectric layer with hollow glass fibers. The buildup layers include dielectric layers below and above the substrate core.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Brandon Christian Marin, Hamid R. Azimi, Sri Chaitra Jyotsna Chavali, Tarek A. Ibrahim, Wei-Lun K Jen, Rahul Manepalli, Kevin T. McCarthy
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Publication number: 20230245940Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Applicant: Intel CorporationInventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11664290Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 27, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 11581271Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.Type: GrantFiled: March 14, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu-Oh Lee, Islam A. Salama, Amruthavalli P. Alur, Wei-Lun K. Jen, Yongki Min, Sheng C. Li
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Patent number: 11552019Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.Type: GrantFiled: March 12, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Haifa Hariri, Amruthavalli P. Alur, Wei-Lun K. Jen, Islam A. Salama
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Patent number: 11443970Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: GrantFiled: February 27, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
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Publication number: 20220199503Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE
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Publication number: 20210391232Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 11158558Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 29, 2016Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210111088Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: April 15, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210035818Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Tarek A. IBRAHIM, Rahul N. MANEPALLI, Wei-Lun K. JEN, Steve S. CHO, Jason M. GAMBA, Javier SOTO GONZALEZ
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Publication number: 20200294938Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Rahul JAIN, Kyu-Oh LEE, Islam A. SALAMA, Amruthavalli P. ALUR, Wei-Lun K. JEN, Yongki MIN, Sheng C. LI
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Publication number: 20200294920Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Inventors: Haifa HARIRI, Amruthavalli P. ALUR, Wei-Lun K. JEN, Islam A. SALAMA
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Publication number: 20200194300Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: ApplicationFiled: February 27, 2020Publication date: June 18, 2020Inventors: Manohar S. KONCHADY, Tao WU, Mihir K. ROY, Wei-Lun K. JEN, Yi LI
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Patent number: 10629469Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: GrantFiled: May 16, 2017Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
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Patent number: 10020262Abstract: In accordance with disclosed embodiments, there are provided high resolution solder resist material for silicon bridge application.Type: GrantFiled: June 30, 2016Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Siddharth K. Alur, Sheng Li, Wei-Lun K. Jen
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Publication number: 20180005946Abstract: In accordance with disclosed embodiments, there are provided high resolution solder resist material for silicon bridge application.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: SIDDHARTH K. ALUR, SHENG LI, WEI-LUN K. JEN
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Publication number: 20170250150Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: ApplicationFiled: May 16, 2017Publication date: August 31, 2017Inventors: Manohar S. KONCHADY, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
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Patent number: 9704735Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: GrantFiled: August 19, 2014Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
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Publication number: 20160056102Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.Type: ApplicationFiled: August 19, 2014Publication date: February 25, 2016Inventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li