Patents by Inventor Wei-Lun LEE
Wei-Lun LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240120288Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate, an encapsulant and an electronic component. The encapsulant is disposed over the substrate, and has a first top surface, a second top surface and a first lateral surface extending between the first top surface and the second top surface. A roughness of the first lateral surface is less than or equal to a roughness of the second top surface. The electronic component is disposed over the second top surface of the encapsulant and electrically connected to the substrate.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Hsin LAI, Chih-Cheng LEE, Shao-Lun YANG, Wei-Chih CHO
-
Publication number: 20240113203Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.Type: ApplicationFiled: January 25, 2023Publication date: April 4, 2024Inventors: Che-Lun CHANG, Wei-Yang LEE, Chia-Pin LIN
-
Publication number: 20240113214Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.Type: ApplicationFiled: March 3, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Lun Chang, Kuan-Ting Pan, Wei-Yang Lee
-
Patent number: 11944412Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.Type: GrantFiled: June 2, 2021Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
-
Publication number: 20240105806Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a V-shape sidewall surface.Type: ApplicationFiled: March 9, 2023Publication date: March 28, 2024Inventors: Che-Lun Chang, Kuan-Ting Pan, Wei-Yang Lee
-
Patent number: 11935805Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 12, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
-
Patent number: 11935781Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Lun Chang, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
-
Patent number: 11916110Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.Type: GrantFiled: July 4, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ching Wang, Wei-Yang Lee, Ming-Chang Wen, Jo-Tzu Hung, Wen-Hsing Hsieh, Kuan-Lun Cheng
-
Publication number: 20180070585Abstract: A laminate including a substrate, an antibacterial agent-containing layer on a surface of the substrate, and a moisture triggering layer on the antibacterial agent-containing layer is provided, wherein the antibacterial agent-containing layer contains a volatile antibacterial agent, and the moisture triggering layer contains a hydrophilic polymer such as polyvinylpyrrolidone. The laminate releases a relatively larger amount of anti-bacterial agent in vapor form in a humid environment in comparison with a dry environment.Type: ApplicationFiled: November 21, 2017Publication date: March 15, 2018Applicant: Food Industry Research and Development InstituteInventors: Yu-Chi Cheng, Hsiang-Ru Li, Wei-Lun Lee, Ying-Cheng Lee, Binghuei Barry Yang
-
Publication number: 20170295780Abstract: A laminate including a substrate, an antibacterial agent-containing layer on a surface of the substrate, and a moisture triggering layer on the antibacterial agent-containing layer is provided, wherein the antibacterial agent-containing layer contains a volatile antibacterial agent, and the moisture triggering layer contains a hydrophilic polymer such as polyvinylpyrrolidone. The laminate releases a relatively larger amount of anti-bacterial agent in vapor form in a humid environment in comparison with a dry environment.Type: ApplicationFiled: June 16, 2016Publication date: October 19, 2017Inventors: Yu-Chi CHENG, Hsiang-Ru LI, Wei-Lun LEE, Ying-Cheng LEE, Binghuei Barry YANG