Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. A shape of a cross-sectional view of the channel member includes a dog-bone shape. By providing the dog-bone shape channel member, a parasitic resistance of the semiconductor device is advantageously reduced, and performance of the semiconductor device may be significantly improved.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: A method includes providing a substrate including a first semiconductor layer over a dielectric layer, thinning the first semiconductor layer, forming a stack of alternating second semiconductor layers and third semiconductor layers over the thinned first semiconductor layer, forming a fin active region protruding from the substrate including a portion of the thinned first semiconductor layer and the stack of alternating second semiconductor layers and third semiconductor layers, forming isolation features over an exposed portion of the dielectric layer, forming a dummy gate stack over the fin active region, forming a source/drain (S/D) recess in the fin active region adjacent to the dummy gate stack, forming an epitaxial S/D feature in the S/D recess, removing the second semiconductor layers to form openings between the third semiconductor layers, and forming a metal gate stack in the openings and in place of the dummy gate stack.

Abstract: A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. A shape of a cross-sectional view of the channel member includes a dog-bone shape. By providing the dog-bone shape channel member, a parasitic resistance of the semiconductor device is advantageously reduced, and performance of the semiconductor device may be significantly improved.

Abstract: A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.