Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.

Abstract: A static random access memory (SRAM) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges the bit information path to the reference voltage.

Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.

Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.

Abstract: A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.

Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.

Abstract: A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.

Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.

Abstract: A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.

Abstract: A semiconductor memory comprises a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for read and write of one or more bits of data to the cross-access dual port bit cell. The semiconductor memory further comprises a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on one or more cross-access dual-port bit cells in the row.

Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract: A method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design, the method includes generating a pattern for the layout based on the circuit design, determining, by a processor, if at least one layout rule is violated by including the generated pattern in the layout and modifying the layout if the at least one layout rule is violated. The at least one layout rule includes a constraint on a relationship between a power line pattern and a device pattern in the layout. The at least one layout rule is specified by comparing a predetermined threshold value with one of an estimated voltage drop along a signal path in a second layout different than the layout or an estimated current density on the signal path in the second layout. The constraint includes a minimum number of contacts per device or power vias per device.

Abstract: An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification.