Patents by Inventor Wei Ning

Wei Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11987431
    Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: May 21, 2024
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
  • Patent number: 11985132
    Abstract: A method of providing continuous user authentication for resource access control includes launching a continuous authentication service at a boot time of a first device, wherein the first device includes a processor, a memory, and one or more sensors configured to collect authentication information. Additionally, the method includes receiving authentication information comprising one or more of explicit authentication information or implicit authentication information, and receiving a request for access to a resource of the first device. Further, the method includes the operations of determining, by the continuous authentication service, a current value of a security state, the current value of the security state based in part on a time interval between a receipt time of the authentication information and a current time and controlling access to the resource based on the current value of the security state.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 14, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haining Chen, Xun Chen, Khaled ElWazeer, Ahmed M. Azab, David Thomson, Ruowen Wang, Wei Yang, Peng Ning
  • Publication number: 20240153997
    Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning CHEN, Pang-Yen Tsai
  • Publication number: 20240130362
    Abstract: A composite solution for enhancing induced disease resistance of lentinan (LNT) to a plant, a preparation method of the composite solution, and a method for enhancing induced disease resistance of LNT to a plant are provided. The composite solution for enhancing induced disease resistance of LNT to a plant includes: an LNT-containing solution and an SPc-containing solution, where SPc is a dendritic macromolecule functionalized by an amino functional group, and has a structural formula shown in formula I, where n=1 to 100. An LNT/SPc complex is produced in the composite solution. SPc spontaneously combines with LNT through hydrogen bonding, such that an agglomerate structure formed by LNT in an aqueous solution is broken and reduced to a nano-scale particle size, and a spherical particle is produced, which can significantly reduce a contact angle of the LNT aqueous solution, and promote the distribution and diffusion of LNT.
    Type: Application
    Filed: August 15, 2023
    Publication date: April 25, 2024
    Applicants: KUNMING CO YUNNAN TOBACCO CO, China Agricultural University
    Inventors: Yonghui XIE, Dekai NING, Zhijiang WANG, Shuo YAN, Wei LI, Jie SHEN, Zhengling LIU, Qinhong JIANG, Youguo ZHAN, Yuanshen WANG, Cun GUO, Sihao WU, Haohao LI
  • Publication number: 20240128125
    Abstract: A method of forming a semiconductor device includes providing a substrate having a recess, and growing an epitaxial feature in the recess. The method of growing the epitaxial feature includes: (a) growing a sub-layer of the epitaxial feature; (b) selectively etching the sub-layer of the epitaxial feature while providing a first UV radiation; and (c) repeating step (a) and step (b) alternately multiple times.
    Type: Application
    Filed: February 1, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Chia-Ling Pai, Pang-Yen Tsai
  • Publication number: 20240126180
    Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 18, 2024
    Inventors: Jang Fung CHEN, Thomas L. LAIDIG, Chung-Shin KANG, Chi-Ming TSAI, Wei-Ning SHEN
  • Publication number: 20240103328
    Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: March 28, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Zhen Zhang, Fuqiang Li, Zhenyu Zhang, Yunping Di, Lizhong Wang, Zheng Fang, Jiahui Han, Yawei Wang, Chenyang Zhang, Chengfu Xu, Ce Ning, Pengxia Liang, Feihu Zhou, Xianqin Meng, Weiting Peng, Qiuli Wang, Binbin Tong, Rui Huang, Tianmin Zhou, Wei Yang
  • Patent number: 11940692
    Abstract: An electronic device includes a substrate, a plurality of first retaining walls, a second retaining wall, and a light emitting element. The first retaining walls are arranged on the substrate. The second retaining wall is arranged on the substrate and disposed within one of the first retaining walls. The light emitting element is arranged on the substrate and disposed between the second retaining wall and one of the first retaining walls adjacent to the second retaining wall. In a cross section, there are a first distance between the light emitting element and the one of the first retaining walls, and a second distance between the light emitting element and the second retaining wall, wherein the second distance is smaller than the first distance.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: March 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Tsung Hsu, Chun-Fang Chen, Wei-Ning Shih
  • Publication number: 20240095141
    Abstract: A method and an apparatus for displaying an information flow on a terminal device, an electronic device, a computer-readable storage medium, and a computer program product are provided. An implementation is: in response to detecting an activation operation on an application for displaying the information flow, reproducing, on the terminal device, a first page displayed on the terminal device when the application is last switched to running in the background or closed; and in response to determining that a time interval between the activation operation and the application being last switched to running in the background or closed does not exceed a first threshold, displaying a second page as a continuation of a content entry displayed in the first page, where the second page includes at least one first content entry cached in the terminal device before the activation operation but not displayed in the first page.
    Type: Application
    Filed: March 21, 2022
    Publication date: March 21, 2024
    Inventors: Yifan ZHANG, Yuqi WANG, Linfei CHU, Jing NING, Kunjie SUN, Yuhang ZHENG, Naifei SONG, Shujuan ZHANG, Lin LIU, Xunzhuo JU, Zhengwei CHEN, Wei ZHANG, Hua ZHANG, Congjun ZHOU, Tingkang WU, Tengfei LV, Hanmeng LIU, Lei WANG
  • Patent number: 11916130
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 27, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Patent number: 11907028
    Abstract: A portable electronic device, including a first body and a second body, is provided. The second body includes a support structure and a display panel. The support structure is pivotally connected to the first body and is connected to the display panel. The support structure has a first bendable portion. An included angle between the first bendable portion and an edge of the support structure is 45 degrees. The support structure is adapted to be bent along the first bendable portion, so that the second body switches between a first mode and a second mode relative to the first body.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 20, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Wen Cheng, Wei-Ning Chai, Ting-Wei Liu, Tzu-Yung Huang, Wang-Hung Yeh
  • Patent number: 11901412
    Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winne Victoria Wei-Ning Chen, Pang-Yen Tsai
  • Patent number: 11869769
    Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning Chen, Andrew Joseph Kelly
  • Patent number: 11852754
    Abstract: System and method of ultrasound imaging methodology are provided. The system and method can include directing an array to transmit sets of cascaded titled ultrasound waves towards a tissue sample, decoding reflected signals through summing, subtracting, and delay operations. The reflected signals can be reconstructed to provide a final decoded output.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 26, 2023
    Assignee: Versitech Limited
    Inventors: Yang Zhang, Yuexin Guo, Wei-Ning Lee
  • Patent number: 11846795
    Abstract: A backlight module includes a substrate, a plurality of light emitting elements, a light guide device and a plurality of reflective elements. The light emitting elements are arranged on the substrate. The light guide device includes a plurality of light guide portions arranged to respectively correspond to the light emitting elements, wherein each of the light guide portions is provided with a first through hole, and the first through holes of the light guide portions respectively expose the light emitting elements. The reflective elements are respectively arranged on the light emitting elements, wherein, in a normal direction of the substrate, the reflective elements respectively overlap with the first through holes of the light guide portions.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: December 19, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Tsung Hsu, Chun-Fang Chen, Wei-Ning Shih
  • Patent number: 11835749
    Abstract: A backlight and a display device are provided herein, which is related to the field of display technology and intends to improve visual effect of the image displayed by the display device. The backlight may include a back plate, a light guide plate and a light source. The back plate includes an accommodation groove, and the light guide plate includes a holding groove at a first side surface of the light guide plate. The light source includes at least one light emitting element. The holding groove is configured to hold at least a portion of the at least one light emitting element, and the accommodation groove is configured to accommodate the light guide plate and the light source.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: December 5, 2023
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ruijun Hao, Long Lian, Tianlei Shi, Wulijibaier Tang, Yuefeng Li, Zhongping Zhao, Xiaojie Wang, Wei Ning, Feixiang Guo, Xuefeng Zhang, Haifang Hu, Yongkai Wu, Le Sun
  • Publication number: 20230352535
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.
    Type: Application
    Filed: June 28, 2023
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Hsuan HSIAO, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE
  • Patent number: 11798945
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 11765564
    Abstract: This document describes low-latency Bluetooth connectivity in a wireless network in which a central node and a peripheral node establish a connection. During a first connection interval, the peripheral node receives a packet from the central node to synchronize communication with the central node, and based on receiving the packet, the peripheral node transmits a first fixed-length packet. If the first fixed-length packet fails to reach the central node, the peripheral node does not receive an acknowledgement, ACK, from the central node during the first connection interval and retransmits the first fixed-length packet during the first connection interval.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 19, 2023
    Assignee: Google LLC
    Inventors: Tapan Pattnayak, Aaron Chen, Wei-Ning Huang, Martin A. Turon
  • Publication number: 20230266616
    Abstract: An electronic device includes a substrate, a plurality of first retaining walls, a second retaining wall, and a light emitting element. The first retaining walls are arranged on the substrate. The second retaining wall is arranged on the substrate and disposed within one of the first retaining walls. The light emitting element is arranged on the substrate and disposed between the second retaining wall and one of the first retaining walls adjacent to the second retaining wall. In a cross section, there are a first distance between the light emitting element and the one of the first retaining walls, and a second distance between the light emitting element and the second retaining wall, wherein the second distance is smaller than the first distance.
    Type: Application
    Filed: January 19, 2023
    Publication date: August 24, 2023
    Inventors: Wei-Tsung HSU, Chun-Fang CHEN, Wei-Ning SHIH