Abstract: Disclosed is a control circuit for a relay in an uninterruptible power supply, comprising a plurality of capacitors comprising at least a first capacitor; and a plurality of relays comprising at least a first relay, a second relay, a third relay and a fourth relay, wherein a first terminal of the first relay is connected to a positive electrode of a battery, a second terminal of the first relay is connected to a first terminal of the first capacitor, a first terminal of the second relay is connected to a negative electrode of the battery, a second terminal of the second relay is connected to a second terminal of the first capacitor, a second terminal of the third relay is connected to the second terminal of the first relay, and a second terminal of the fourth relay is connected to the second terminal of the second relay.

Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

Abstract: A transparent display panel has a plurality of sub-pixel regions, which are divided into at least two display unit groups. The transparent display panel includes a first substrate and a second substrate assembled with each other, and a light exit control layer disposed therebetween. The first substrate includes a first base and a dimming component disposed on a side of the first base. The dimming component includes a plurality of dimming lenses. Each dimming lens is configured to transmit exit light of one sub-pixel region to human eyes and focus the exit light on a corresponding focal plane. The plurality of dimming lenses are configured to focus exit light of the at least two display unit groups on different focal planes. The focal planes are located at a side of the transparent display panel away from the human eyes.

Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.

Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: In an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.

Abstract: Disclosed herein is drawn to a method for producing a nanoframe of Prussian blue (PB) or an analogue thereof (PBA). The producing method comprises: (a) mixing a nanocube of PB or PBA with an acid solution to form a mixture; and (b) heating the mixture of the step (a) in an oil bath at 80-100° C. for 0.5 hours-1 month to produce the nanoframe of PB or PBA. Also encompassed herein is a method for treating a cancer in a subject in need thereof, which comprises administering an effective amount of a nanocube or a nanoframe of PB or PBA to the subject.

Abstract: A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Abstract: A display substrate and a display device. The display substrate includes a pixel circuit in which the driving circuit controls a driving current driving the light emitter element to emit light; the first light emission control circuit applies a first voltage to a first terminal of the driving circuit in response to a first light emission control signal; the second light emission control circuit applies the driving current to the light emitter element in response to a second light emission control signal; the first reset circuit applies a first reset voltage to the control terminal of the driving circuit in response to a first reset signal; the first reset signal and the first light emission control signal are simultaneously turn-on signals during a period; the first light emission control line and the second light emission control line extend along a first direction and are arranged in a second direction.

Abstract: The present disclosure provides a package structure having a photonic integrated circuit, the package structure includes a substrate, a chip and an optical module. The chip has an optical waveguide structure and a recessed portion. The optical waveguide structure is adjacent to the recessed portion. The recessed portion faces the substrate, and the chip is engaged to the substrate by flip chip. The optical module is provided in the recessed portion of the chip.

Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

Abstract: In an embodiment, a set of texts associated with a domain is received. A set of hypothesis statements associated with the domain is received. A pre-trained natural language inference (NLI) model is applied on each of the received set of texts and on each of the received set of hypothesis statements. A second text corpus associated with the domain is generated. The generated second text corpus corresponds to a set of labels associated with the domain. A few-shot learning model is applied on the generated second text corpus to generate a third text corpus associated with the domain. The generated third text corpus is configured to fine-tune the applied pre-trained NLI model, and the fine-tuned NLI model is configured to label an input text associated with the domain. A display of the labelled input text on a display device is controlled.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor; forming a plurality of first metal strips above the plurality of gate strips; and forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view; wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.

Abstract: Various systems and methods are described for implementing trust authority or trust attestation verification operations, including for Trust-as-a-Service or Attestation-as-a-Service implementations, in accordance with the techniques discussed herein. In various examples, operations and configurations are described to enable service-to-service attestation using a trust authority, to operate an attestation service, and to coordinate trust operations between relying and requesting parties.

Abstract: A method of manufacturing a plurality of via structures includes providing an integrated circuit (IC) photo mask including via features and assist features positioned exclusively along alternating diagonal grid lines of a grid, aligning the IC photo mask with first metal segments of a first metal layer of a semiconductor substrate, the first metal segments having a first spacing corresponding to a first pitch of the grid, performing one or more photolithography processes including the IC photo mask, thereby defining via structure locations corresponding to the via features, and forming via structures at the defined via structure locations.

Abstract: Disclosed embodiments herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

Abstract: A compound is provided as having a structure of Formula I: where X1 and X2 are each independently a nitrogen atom or a C—R group, C is a carbon atom, R is a hydrogen atom, a deuterium atom, a halogen atom, or a cyano group, CR, and at least one of X1 and X2 is N; L1, L2, and L3 are each independently a single bond, a substituted or unsubstituted aryl group, or substituted or unsubstituted aryl heteroaryl group; and Ar1, Ar2 are each independently a substituted or unsubstituted aryl group or a substituted or unsubstituted heteroaryl group.

Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.