Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

Abstract: A semiconductor device includes a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes recesses in the second surface, and surfaces of each of the recesses are wet etched surfaces. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.

Abstract: A semiconductor device includes a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes recesses in the second surface, and surfaces of each of the recesses are wet etched surfaces. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.

Abstract: A semiconductor device includes a carrier, a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes inverted pyramid recesses in the second surface. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.

Abstract: A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

Abstract: A semiconductor device includes a carrier, a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes inverted pyramid recesses in the second surface. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.

Abstract: A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.

Abstract: A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.

Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.

Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.