Abstract: A power management device includes a pulse-width modulation (PWM) circuit, a pulse-frequency modulation (PFM) circuit, a first switch, a second switch, an overcurrent protection circuit, a current detection circuit, and a short-circuit detection circuit. The PWM/PFM circuit is enabled by a short-circuit detection signal and generates a PWM/PFM signal. The first/second switch is electrically coupled between a high-voltage/low-voltage terminal and an output node, and provides a first/second output current for the output node according to the PWM/PFM signal. The overcurrent protection circuit makes the PWM/PFM circuit turn off the first switch and turn on the second switch when the first output current reaches a current threshold. The current detection circuit makes the PWM/PFM circuit turn off the second switch when the second output current reaches zero and then turn on the first switch.

Abstract: A regulator device includes a first switch, a second switch, and a controlling circuit. A control terminal of the first switch is configured to receive a first control signal. A first terminal of the second switch is coupled with a second terminal of the first switch at a node. A control terminal of the second switch is configured to receive a second control signal. The controlling circuit is coupled to the control terminal of the first switch, the control terminal of the second switch, and the node. The controlling circuit outputs the first control signal with a first slope to the first switch during a first period, and outputs the first control signal with a second slope to the first switch during a second period. The first period is less than the second period, and the first slope is larger than the second slope.

Abstract: A buck-boost switching regulating method includes outputting a mode signal according to an input voltage and an output voltage, generating one of a plurality of triangle waves according to the mode signal, comparing a feedback signal and a reference signal to generate an error signal, comparing the error signal and the generated triangle wave to output a comparison signal, and generating a set of switch signals according to the comparison signal. The feedback signal is related to the output voltage. The waveform of the triangle wave generated when the mode signal represents a buck-boost mode is larger than that when the mode signal represents a adjusting mode.

Abstract: A regulator device includes a first switch, a second switch, a protecting circuit, and a driving circuit. The first switch is configured to receive power supply voltage. One terminal of the second switch and the first switch are coupled at a node. The other terminal of the second switch is coupled to ground. The protecting circuit is coupled to the node, and outputs at least one protecting signal according to the turn on/off state of the first switch and the second switch and the voltage of the node. The driving circuit is coupled to the first switch, the second switch, and the protecting circuit, and turns off the first switch or the second switch according the at least one protecting signal.

Abstract: A regulator device includes a first switch, a second switch, a protecting circuit, and a driving circuit. The first switch is configured to receive power supply voltage. One terminal of the second switch and the first switch are coupled at a node. The other terminal of the second switch is coupled to ground. The protecting circuit is coupled to the node, and outputs at least one protecting signal according to the turn on/off state of the first switch and the second switch and the voltage of the node. The driving circuit is coupled to the first switch, the second switch, and the protecting circuit, and turns off the first switch or the second switch according the at least one protecting signal.

Abstract: A regulator device includes a first switch, a second switch, and a controlling circuit. A control terminal of the first switch is configured to receive a first control signal. A first terminal of the second switch is coupled with a second terminal of the first switch at a node. A control terminal of the second switch is configured to receive a second control signal. The controlling circuit is coupled to the control terminal of the first switch, the control terminal of the second switch, and the node. The controlling circuit outputs the first control signal with a first slop to the first switch during a first period, and outputs the first control signal with a second slop to the first switch during a second period. The first period is less than the second period, and the first slope is larger than the second slope.

Abstract: A ripple suppressor suppresses ripples of a channel current. The ripple suppressor comprises a voltage-controlled current source, a stabilizer, and an auto-calibration circuit. A control voltage at a control node controls the channel current flowing through a path connecting first and second channel nodes. The voltage-controlled current source receives a current-setting signal to generate the control voltage, so as to stabilize the channel current in response to the current-setting signal. The stabilizer at least provides low-pass filtering to generate and stabilize the current-setting signal in response to a first channel voltage at the first channel node. The auto-calibration circuit controls the stabilizer in response to the control voltage, so as to make the control voltage in compliance with a first predetermined condition.

Abstract: A ripple suppressor suppresses ripples of a channel current. The ripple suppressor comprises a voltage-controlled current source, a stabilizer, and an auto-calibration circuit. A control voltage at a control node controls the channel current flowing through a path connecting first and second channel nodes. The voltage-controlled current source receives a current-setting signal to generate the control voltage, so as to stabilize the channel current in response to the current-setting signal. The stabilizer at least provides low-pass filtering to generate and stabilize the current-setting signal in response to a first channel voltage at the first channel node. The auto-calibration circuit controls the stabilizer in response to the control voltage, so as to make the control voltage in compliance with a first predetermined condition.

Abstract: A control circuit of light emitting diodes is used for driving at least one series of light emitting diodes. The control circuit includes a current setting pin, a driving current generator, a regulator circuit, and an adjuster. A reference current flows through the current setting pin. The driving current generator is used for generating a driving current flowing through the series of light emitting diodes according to the reference current. The adjuster generates an adjustment voltage according to the reference current. Then, the regulator circuit generates a supply voltage to drive the series of light emitting diodes, and regulates a voltage of a first terminal of the series of light emitting diodes at a target voltage according to the adjustment voltage. The target voltage is increased with decrease of the driving current when the driving current is less than a first predetermined current.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory device involving the steps of forming a gate oxide layer on a substrate; forming a first poly layer over the gate oxide layer; forming an insulating layer over the first poly layer, the insulating layer comprising a first oxide layer over the first poly layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second poly layer over the insulating layer; forming a tungsten silicide layer over the second poly layer; etching a portion of the tungsten silicide layer and the second poly layer, wherein in the etched portion at least about 20% of the second poly is not etched, thereby partially defining at least one stacked gate structure; etching at least a portion of the insulating layer and the unetched portion of the second poly layer thereby defining at least one select gate transistor structure; forming an interlayer dielectric layer over the select gate transistor structu