Abstract: Disclosed is a clock generating circuit capable of operating in an analog clock data recovery (ACDR) mode to reduce the loop latency or a clock multiplication unit (CMU) mode to suppress reference jitter. The circuit includes a filter and an oscillator. The filter receives an input signal to determine voltages of a first node and a second node respectively and includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal. The second filtering circuit includes a switch and a capacitor connected in series, wherein the second node is between the switch and capacitor, and the switch is turned off in the ACDR mode and turned on in the CMU mode. The oscillator outputs a clock according to the first node's voltage in the ACDR mode or according to the second node's voltage in the CMU mode.

Abstract: Disclosed is a clock generating circuit including a filter and a ring oscillator. The filter receives an input signal and accordingly determines a first voltage signal and a second voltage signal that are outputted via a first node and a second node respectively. The filter includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal; the second filtering circuit includes a switch and a capacitor connected in series, in which the second node is between the switch and the capacitor, and the switch is turned off in an analog clock data recovery (ACDR) mode and turned on in a clock multiplication unit (CMU) mode. The ring oscillator outputs at least one clock according to the first voltage signal in the ACDR mode and outputs at least one clock according to the second voltage signal in the CMU mode.