Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: An electronic apparatus and a hotkey prompt method thereof are provided. The method includes the following steps. A power-on self-test (POST) procedure of a basic input output system (BIOS) is performed. During the POST procedure, a display panel of a keyboard module is controlled to display a first keyboard layout, so as to display at least one hotkey corresponding to at least one hotkey function of the BIOS via the display panel. After a hotkey input operation is received via the keyboard, a first hotkey function of the at least one hotkey function of the BIOS is performed. The hotkey input operation is used to enable the first hotkey function. In response to performing the first hotkey function, the display panel of the keyboard module is controlled to display a second keyboard layout.

Abstract: A high hardness and temperature-resistant alloy is disclosed, and comprises 10-40 atomic percent Co, 30-56 atomic percent Cr, 10-40 atomic percent Ni, 6-13 atomic percent C, 0-8 atomic percent Mo, and 0-8 atomic percent W. Moreover, the elemental composition of the high hardness and temperature-resistant alloy can further comprise at least one additive element, such as Pb, Sn, Ge, Si, Zn, Sb, P, B, Mg, Mn, V, Nb, Ti, Zr, Y, La, Ce, Al, Ta, Cu, and Fe. Experimental data reveal that, the high hardness and temperature-resistant alloy can still show a property of hardness greater than HV100 in 900 degrees Celsius. Therefore, experimental data have proved that the high hardness and temperature-resistant alloy has a significant potential for applications in the manufacture of hot working die metals, components (e.g., turbine blade) for high temperature applications, and devices (e.g., aeroengine) for high temperature applications.

Abstract: Described are a system, method, and computer program product for debiasing embedding vectors of machine learning models. The method includes receiving embedding vectors and generating two clusters thereof. The method includes determining a first mean vector of the first cluster and a second mean vector of the second cluster. The method includes determining a bias associated with each of a plurality of first candidate vectors and replacing the first mean vector with a first candidate vector based on the bias. The method includes determining a bias associated with each of a plurality of second candidate vectors and replacing the second mean vector with a second candidate vector based on the bias. The method includes repeatedly replacing the first and second mean vectors until an extremum of the bias score is reached, and debiasing the embedding vectors by linear projection using a direction defined by the first and second mean vectors.

Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Abstract: Apparatuses and methods for calculating heart rate are disclosed herein. The apparatus can include a processor configured to calculate heart rate information. The processor includes a heart rate calculator including a memory configured to store a PPG signal and a calculation element coupled to the memory and configured to calculate a heart rate value and generate at least one quality checking factor according to the PPG signal. The processor also includes a checking element configured to determine a validity indicator according to the at least one quality checking factor, a memory control element coupled to the memory and configured to access the memory to transmit the PPG signal, and a multiplexer configured to output the PPG signal accessed by the memory control element or the heart rate value calculated by the calculation element according to the validity indicator.

Abstract: Provided is a system for analyzing features associated with entities using an embedding tree, the system including at least one processor programmed or configured to receive a dataset associated with a plurality of entities, wherein the dataset comprises a plurality of data instances for a plurality of entities. The processor may be programmed or configured to generate at least two embeddings based on the dataset and determine split criteria for partitioning an embedding space of at least one embedding tree associated with the dataset based on feature data associated with an entity and embedding data associated with the at least two embeddings. The processor may be programmed or configured to generate at least one embedding tree having a plurality of nodes based on the split criteria. Methods and computer program products are also provided.

Abstract: A two-phase immersion-type heat dissipation structure having acute-angle notched structures is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins has first and second surfaces defined thereon and connected to each other. An angle between the first surface and the fin surface is from 80 degrees to 100 degrees, and an angle between the second surface and the fin surface is less than 75 degrees.

Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.

Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.

Abstract: A two-phase immersion-cooling heat-dissipation composite structure is provided. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.

Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.

Abstract: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Abstract: An optical detector module can be used to implement proximity sensing function by detecting ambient light outside of the optical detector module in accordance with a first detection threshold. An optical detector module can be further used to implement other active functions such as material detection (e.g., skin) or depth-sensing by emitting one or more optical signals (e.g., light pulses at a specific wavelength) and detecting the reflected optical signals relative to a second and/or third detection threshold. The disclosure provides technical solutions for actively monitoring detection threshold(s) of an optical detector module to achieve better power management. In some embodiments, such solutions are useful for photodetectors having a wide sensing bandwidth, such as a photodetector formed in germanium or a photodetector comprising an absorption region comprising germanium.