Patents by Inventor Wei-Yen Woon
Wei-Yen Woon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240047523Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer over first sidewalls of the gate stack using a first precursor. The first precursor includes a first boron- and nitrogen-containing material having a first hexagonal ring structure, the spacer has a plurality of first layers, and each first layer includes boron and nitrogen.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Ming LIN, Szu-Hua CHEN, Wei-Yen WOON, Szuya LIAO
-
Publication number: 20240038595Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Kan HU, Jhih-Rong HUANG, Yi-Bo LIAO, Shuen-Shin LIANG, Min-Chiang CHUANG, Sung-Li WANG, Wei-Yen WOON, Szuya LIAO
-
Publication number: 20240030281Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hua Chen, Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Ming-Jie Huang, Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Szuya Liao
-
Publication number: 20240014282Abstract: A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.Type: ApplicationFiled: January 26, 2023Publication date: January 11, 2024Inventors: Kuan-Kan HU, Tsung-Kai CHIU, Wei-Yen WOON, Szuya LIAO, Ku-Feng YANG
-
Publication number: 20230402386Abstract: A semiconductor device includes a substrate and an interconnection layer disposed on the substrate. The interconnection layer includes a plurality of etch-stop layers, a plurality of first dielectric layers, and a plurality of conductive layers. The first dielectric layers are disposed on the plurality of etch-stop layers, wherein the plurality of first dielectric layers comprises porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The conductive layers are embedded in the first dielectric layers.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hua Chen, Wei-Yen Woon, Szuya Liao
-
Publication number: 20230402528Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.Type: ApplicationFiled: March 2, 2023Publication date: December 14, 2023Inventors: Szu-Hua Chen, Cheng-Ming Lin, Wei-Xiang You, Wei-De Ho, Wei-Yen Woon, Szuya Liao
-
Publication number: 20230317674Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.Type: ApplicationFiled: January 6, 2023Publication date: October 5, 2023Inventors: Che Chi SHIH, Cheng-Ting CHUNG, Han-Yu LIN, Wei-Yen WOON, Szuya LIAO
-
Publication number: 20230282715Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhih-Rong HUANG, Mrunal Abhijith KHADERBAD, Yi-Bo LIAO, Yen-Tien TUNG, Wei-Yen WOON
-
Publication number: 20230268386Abstract: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Yu LIN, Che-Chi SHIH, Szu-Hua CHEN, Kuan-Da HUANG, Cheng-Ming LIN, Tze-Chung LIN, Li-Te LIN, Wei-Yen WOON, Pinyen LIN
-
Publication number: 20230020731Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.Type: ApplicationFiled: November 23, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
-
Publication number: 20230010280Abstract: An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.Type: ApplicationFiled: May 6, 2022Publication date: January 12, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith KHADERBAD, Wei-Yen WOON
-
Publication number: 20230009745Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Ming LIN, Han-Yu LIN, Wei-Yen WOON, Mrunal Abhijith KHADERBAD
-
Publication number: 20220310800Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.Type: ApplicationFiled: November 23, 2021Publication date: September 29, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Wei-Yen WOON, Cheng-Ming LIN, Han-Yu LIN, Szu-Hua CHEN
-
Publication number: 20220293736Abstract: The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.Type: ApplicationFiled: November 16, 2021Publication date: September 15, 2022Inventors: Mrunal Abhijith Khaderbad, Dhayakumar Mahaveer Sathaiya, Wei-Yen Woon
-
Publication number: 20220285515Abstract: The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of FETs, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.Type: ApplicationFiled: December 14, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith KHADERBAD, Wei-Yen Woon
-
Publication number: 20220285221Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.Type: ApplicationFiled: December 14, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen, Jhih-Rong Huang, Tzer-Min Shen
-
Patent number: 11011340Abstract: The present invention relates to an ion generation composite target for an ion irradiation technology including: a substrate having a through hole formed thereon; and a graphene thin film configured on the substrate, across the through hole, having a thickness in a range between 1 nm to 3 nm, and ionized to release a proton or a carbon ion.Type: GrantFiled: November 19, 2019Date of Patent: May 18, 2021Assignee: National Central UniversityInventors: Wei-Yen Woon, Kuramitsu Yasuhiro
-
Publication number: 20210035768Abstract: The present invention relates to an ion generation composite target for an ion irradiation technology including: a substrate having a through hole formed thereon; and a graphene thin film configured on the substrate, across the through hole, having a thickness in a range between 1 nm to 3 nm, and ionized to release a proton or a carbon ion.Type: ApplicationFiled: November 19, 2019Publication date: February 4, 2021Applicant: National Central UniversityInventors: Wei-Yen WOON, Kuramitsu YASUHIRO
-
Patent number: 9899214Abstract: The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.Type: GrantFiled: June 13, 2017Date of Patent: February 20, 2018Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Jenq-Horng Liang, Hsu-Sheng Tsai, Wei-Yen Woon
-
Patent number: 8404546Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.Type: GrantFiled: October 14, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin