Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.

Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.

Abstract: A photoresist includes a polymer and a photoactive compound. The photoactive compound contains a sensitizer component. The photoactive compound contains an acid generator or a base molecular. The acid generator or the base molecular bonds the sensitizer component. The photoactive compound is within a polymer backbone. The sensitizer component is configured to absorb an EUV light to produce electrons.

Abstract: A convertible information handling system comprising an antenna feed operatively coupled to a wireless adapter and an hinged adjustable antenna spanning a hinge for communicating on a wireless link, the hinge pivoting between a first antenna portion of the hinged adjustable antenna on a display chassis and a second antenna portion of an hinged adjustable antenna on a base chassis and the hinge which rotates the convertible information handling system between a first configuration and a tablet configuration and a first adjustable antenna configuration in the first configuration and a second adjustable antenna configuration in the tablet configuration, where the first adjustable antenna configuration supports a first bandwidth at the wireless adapter and the second adjustable antenna configuration supports a second bandwidth at the wireless adapter.

Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.

Abstract: A power-adjusting method for uplink transmission is provided. The power-adjusting method is applied to user equipment (UE). In response to the UE transmitting a first packet carrying a specific message to a network node, the power-adjusting method includes the UE increasing the transmission power to transmit the first packet.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, from a base station, a configuration specifying an initial aggregated bandwidth W0 carried on C0 component carriers on which a reception unit (RXU) of the UE is to receive signals. The UE determines a total bandwidth WTOT on which the UE is capable of receiving signals. The UE determines, based on WTOT and W0, an initial hardware limit of Q0? RXUs that the UE is allowed to activate concurrently. The UE determines an adjusted aggregated bandwidth W1 carried on C1 component carriers on which an RXU of the UE is to receive signals based on a channel condition between the UE and the base station.

Abstract: A method for transporting a cassette pod for containing semiconductor wafers is provided. The method includes transporting a cassette pod configured to receive a semiconductor wafer with a transporting apparatus. The method further includes supplying a gas from a cylinder into a housing of the cassette pod. The cylinder is externally positioned on the housing. The method also includes detecting a gas pressure in the cylinder with a detection element. In addition, the method includes issuing a signal to the transporting apparatus when the gas pressure in the cylinder is lower than a predetermined limit.

Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.

Abstract: A method for transporting a cassette pod for containing semiconductor wafers is provided. The method includes transporting a cassette pod configured to receive a semiconductor wafer with a transporting apparatus. The method further includes supplying a gas from a cylinder into a housing of the cassette pod. The cylinder is externally positioned on the housing. The method also includes detecting a gas pressure in the cylinder with a detection element. In addition, the method includes issuing a signal to the transporting apparatus when the gas pressure in the cylinder is lower than a predetermined limit.

Abstract: A method for transporting a cassette pod for containing semiconductor waters is provided. The method includes transporting a cassette pod configured to receive a semiconductor wafer with a transporting apparatus. The method further includes supplying a gas from a cylinder into a housing of the cassette pod. The cylinder is externally positioned on the housing. The method also includes detecting a gas pressure in the cylinder with a detection element. In addition, the method includes issuing a signal to the transporting apparatus when the gas pressure in the cylinder is lower than a predetermined limit.

Abstract: A method for transporting a cassette pod for containing semiconductor waters is provided. The method includes transporting a cassette pod configured to receive a semiconductor wafer with a transporting apparatus. The method further includes supplying a gas from a cylinder into a housing of the cassette pod. The cylinder is externally positioned on the housing. The method also includes detecting a gas pressure in the cylinder with a detection element. In addition, the method includes issuing a signal to the transporting apparatus when the gas pressure in the cylinder is lower than a predetermined limit.