Patents by Inventor Wei-Yuan Lu
Wei-Yuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961912Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.Type: GrantFiled: June 6, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
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Patent number: 11862712Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.Type: GrantFiled: November 12, 2020Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Chung-Chi Wen, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20230387305Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20230387108Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Te LIN, Wei-Yuan LU, Feng-Cheng YANG
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Publication number: 20230378270Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
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Patent number: 11824121Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.Type: GrantFiled: March 27, 2023Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20230361116Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.Type: ApplicationFiled: July 19, 2023Publication date: November 9, 2023Inventors: Wei-Yuan LU, Sai-Hooi YEONG
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Patent number: 11798941Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.Type: GrantFiled: November 16, 2020Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yuan Lu, Sai-Hooi Yeong
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Patent number: 11791335Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.Type: GrantFiled: May 21, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Te Lin, Wei-Yuan Lu, Feng-Cheng Yang
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Patent number: 11791402Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.Type: GrantFiled: May 14, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chia-Pin Lin
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Patent number: 11784222Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.Type: GrantFiled: January 10, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
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Publication number: 20230231053Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.Type: ApplicationFiled: March 27, 2023Publication date: July 20, 2023Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20230207653Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.Type: ApplicationFiled: May 20, 2022Publication date: June 29, 2023Inventors: Szu-Wei Tseng, Wei-Yuan Lu, Wei-Yang Lee, Chia-Pin Lin, Tzu-Wei Kao
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Patent number: 11616142Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.Type: GrantFiled: December 6, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20220367622Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.Type: ApplicationFiled: November 18, 2021Publication date: November 17, 2022Inventors: Yan-Ting Lin, Wei-Jen Lai, Chien-I Kuo, Wei-Yuan Lu, Chia-Pin Lin, Yee-Chia Yeo
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Publication number: 20220367670Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.Type: ApplicationFiled: May 14, 2021Publication date: November 17, 2022Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chia-Pin Lin
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Publication number: 20220359769Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
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Publication number: 20220352353Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.Type: ApplicationFiled: July 20, 2022Publication date: November 3, 2022Inventors: Feng-Ching Chu, Chung-Chi WEN, Wei-Yuan LU, Feng-Cheng YANG, Yen-Ming CHEN
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Patent number: 11489078Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.Type: GrantFiled: October 27, 2020Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
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Publication number: 20220302299Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su