Abstract: A scan output flip-flop includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal to serve as an input signal. The control circuit is controlled by a first clock signal and a second clock signal to generate a first control signal and a second control signal according to the input signal. The scan-out stage circuit receives only one of the first control signal and the second control signal, and is controlled by the first test enable signal and a second test enable signal to generate a scan-out signal.

Abstract: A scan output flip-flop includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal to serve as an input signal. The control circuit is controlled by a first clock signal and a second clock signal to generate a first control signal and a second control signal according to the input signal. The scan-out stage circuit receives only one of the first control signal and the second control signal, and is controlled by the first test enable signal and a second test enable signal to generate a scan-out signal.

Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Abstract: An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).

Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

Abstract: An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.

Abstract: A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.

Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

Abstract: An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).

Abstract: A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.

Abstract: An antifuse-type one time programming memory cell, comprising: a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with a bit line, and a gate terminal of the first select transistor is connected with a word line; an antifuse transistor, wherein a first drain/source terminal of the antifuse transistor is connected with a second drain/source terminal of the first select transistor, and a gate terminal of the antifuse transistor is connected with an antifuse control line; and a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the antifuse transistor, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with the bit line.

Abstract: A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

Abstract: An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.

Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

Abstract: A one time programming memory cell includes a selecting circuit, a first antifuse storing circuit and a second antifuse storing circuit. The selecting circuit is connected with a bit line and a word line. The first antifuse storing circuit is connected between a first antifuse control line and the selecting circuit. The second antifuse storing circuit is connected between a second antifuse control line and the selecting circuit.

Abstract: A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.