Abstract: Embodiments of this application provide a page drawing control method, apparatus, and device. The method includes: obtaining a drawing instruction for a first page, where the drawing instruction is used to instruct to draw the first page, the first page includes a first control, and the first control includes at least one child control; and if it is determined that an image corresponding to the first control exists and the first control and the child control in the first control are not updated, drawing the first control based on the image corresponding to the first control, or if it is determined that an image corresponding to the first control does not exist or the first control or the child control in the first control is updated, generating the image corresponding to the first control and drawing the first control. In this way, page drawing efficiency is improved.

Abstract: An operation method of a direct memory access (DMA) circuit comprising a buffer circuit and two channels includes following steps: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of first and second channels that respectively correspond to first and second data; determining a read address according to the first start address and a read count; reading a first part of the first data from the buffer circuit according to the read address and updating the read count; reading at least one part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count; and reading a second part of the first data from the buffer circuit according to the updated read address.

Abstract: An array substrate has a display area and a bezel area located on at least one side of the display area. The bezel area includes a bonding region. The array substrate includes a substrate, a plurality of signal lines, a plurality of conductive bumps, and an insulating layer. The signal lines are disposed on the substrate. The conductive blocks are disposed on a portion of the substrate located in the bonding region, and a conductive bump is connected to at least one signal line. The insulating layer covers the plurality of signal lines and is located between every two adjacent conductive bumps. The conductive bump includes a conductive metal layer. A distance from a surface of the conductive metal layer away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate.

Abstract: A neutron capture therapy system is provided, which may prevent a material of a beam shaping assembly from deformation and damaged, and improve the flux and quality of neutron sources. A boron neutron capture therapy system (100) includes a neutron generating device (10) and a beam shaping assembly (20). The neutron generating device (10) includes an accelerator (11) and a target (T). A charged particle beam (P) generated by acceleration of the accelerator (11) acts with the target (T) to generate neutrons. The neutrons form a neutron beam (N). The neutron beam (N) defines a main axis (X). The beam shaping assembly (20) includes a support part (21) and a main part (23) filled within the support part (21).

Abstract: A silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) structure is provided, including a substrate layer; a buried oxide layer which is arranged on an upper surface of the substrate layer and is made of SiO2; an active zone which is arranged on an upper surface of the buried oxide layer; a source electrode and a drain electrode which are arranged on an upper surface of the active zone; a gate dielectric layer which is arranged between the source electrode and the drain electrode; a gate electrode which is provided in the gate dielectric layer; and a heat conduction column which penetrates through the buried oxide layer, and its top wall is in contact with the active zone. The heat conduction column dissipates heat in the active zone, resulting in a lattice temperature of the active zone will not increase extremely and avoiding a decrease of a current of the drain electrode.

Abstract: A silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) structure is provided, including a substrate layer; a buried oxide layer which is arranged on an upper surface of the substrate layer and is made of SiO2; an active zone which is arranged on an upper surface of the buried oxide layer; a source electrode and a drain electrode which are arranged on an upper surface of the active zone; a gate dielectric layer which is arranged between the source electrode and the drain electrode; a gate electrode which is provided in the gate dielectric layer; and a heat conduction column which penetrates through the buried oxide layer, and its top wall is in contact with the active zone. The heat conduction column dissipates heat in the active zone, resulting in a lattice temperature of the active zone will not increase extremely and avoiding a decrease of a current of the drain electrode.

Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.

Abstract: The method of forming the semiconductor structure includes the following steps. Bit line structures are formed on a substrate. A first liner is formed on the bit line structures. A second liner is formed on the first liner. A portion of the second liner is removed to expose a portion of the top surface of the first liner. A portion of the first liner is removed to form a space between each bit line structure and the second liner and form a remaining first liner. A sealing material is formed at the opening of the space to form an air gap between each bit line structure and the second liner.

Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.

Abstract: A pharmaceutical composition that is effective in relieving pain from joint and muscle strain is disclosed herein. The pharmaceutical composition comprises a combination of Pecan kernels; Eucommia ulmoides barks; and Psoralea corylifolia seeds as it active ingredients.

Abstract: Disclosed is a bilayer bionic drug-loaded hydrogel, and preparation and application thereof. The hydrogel includes: an outer-layer hydrogel and an inner-layer hydrogel. The outer-layer hydrogel is prepared by: forming a polyvinyl alcohol hydrogel by directionally freezing a polyvinyl alcohol aqueous solution, soaking the polyvinyl alcohol aqueous solution in a sodium sulfate solution, and removing salt ions after soaking; and the inner-layer hydrogel is prepared by components of: a loaded drug, polyvinyl alcohol, chitosan, genipin, water, and a pH adjuster. The hydrogel of the present disclosure can be applied to deeply infected areas of wounds in open war wounds, and has protective, anti-inflammatory, haemostatic, reparative, anti-drug resistant bacterial effects, and other properties.

Abstract: A multi-phase inductor structure is provided. The multi-phase inductor structure includes a first magnetic core, two second magnetic cores, and two first electrical conductors. The two second magnetic cores are respectively arranged on opposite sides of the first magnetic core, and each have a first engagement surface. A first annular convex wall and a first upright convex wall are formed on the first engagement surface, and a first recess is formed therebetween. The two first electrical conductors are respectively arranged in two of the first recesses of the first engagement surface, and each have has a first body and two first pins that are respectively connected to two ends of the first body. The two first pins extend in opposite directions. A magnetic permeability of the first magnetic core is different from a magnetic permeability of each of the two second magnetic cores.

Abstract: A method is provided for dynamically determining measurement uncertainty (MU) of a measurement device for measuring a signal output by a device under test (DUT). The method includes storing characterized test data in a nonvolatile memory in the measurement device, the characterized test data being specific to the measurement device for a plurality of sources of uncertainty; receiving a parameter value of the DUT; measuring the signal output by the DUT and received by the measurement device; and calculating the measurement uncertainty of the measurement device for measuring the received signal using the stored characterized test data and the received parameter value of the DUT.

Abstract: A thermosiphon heat exchanger includes a chassis, an evaporation assembly and a condensation assembly. The chassis has an internal circulation chamber and an external circulation chamber separated from each other. The evaporation assembly is disposed in the internal circulation chamber. The condensation assembly is disposed in the external circulation chamber and horizontally positioned higher than the evaporation assembly, and the condensation assembly is coupled to the evaporation assembly by plural separated loops.

Abstract: A thermosiphon heat exchanger includes a chassis, an evaporation assembly and a condensation assembly. The chassis has an internal circulation chamber and an external circulation chamber separated from each other. The evaporation assembly is disposed in the internal circulation chamber. The condensation assembly is disposed in the external circulation chamber and horizontally positioned higher than the evaporation assembly, and the condensation assembly is coupled to the evaporation assembly by plural separated loops.

Abstract: An endoscope includes: an imaging device chip having a chip connection portion; a tubular housing tube used to a scope tip portion of an endoscope; a substrate to which the imaging device chip is fixed, the substrate having a substrate connection portion, the substrate being capable of bending at near the substrate connection portion when the substrate is inserted into the housing tube; a lead wire connecting the substrate connection portion and the chip connection portion; flexible and non-conductive resin covering an entirety of the lead wire; and an imaging module including the substrate provided with the imaging device chip thereon, the imaging module inserted into the housing tube.

Abstract: A data storage method and apparatus. The method includes: determining a same column attribute of at least two data objects that are to be stored in a KeyValue type distributed database; determining a format of a row identifier of each data object of the at least two data objects, where the row identifier format includes the same column attribute and a data object identifier; determining a row identifier value of each data record of each data object according to the determined row identifier format of each data object; and storing each data record and the row identifier value of each data record, where the row identifier value of each data record is used as a primary index. The data storage method and apparatus in embodiments of the present invention can improve data query efficiency.

Abstract: A training data set for training a machine learning module is prepared by dividing normal files and malicious files into sections. Each section of a normal file is labeled as normal. Each section of a malicious file is labeled as malicious regardless of whether or not the section is malicious. The sections of the normal files and malicious files are used to train the machine learning module. The trained machine learning module is packaged as a machine learning model, which is provided to an endpoint computer. In the endpoint computer, an unknown file is divided into sections, which are input to the machine learning model to identify a malicious section of the unknown file, if any is present in the unknown file.

Abstract: A base cell of a gate array architecture includes an increased number of transistors that can be interconnected or not interconnected so as to realize similar advantages as a having a library of transistors of different sizes. In one embodiment, each column a base cell contains two PMOS transistors and two NMOS transistors connected so as to share a single polysilicon (“poly”) gate electrode. Such an arrangement of the transistors in metal only programmable base cell architecture provides three different P and N transistor widths per poly gate and may provide nine different combinations transistor widths for P and N for design. The number of gate electrodes is minimized and their arrangement simplified such that the size of the base cell may be same size compared to traditional gate array base cell with four transistors. Moreover, only a single type of base cell need be provided, simplifying layout and design.

Abstract: A training data set for training a machine learning module is prepared by dividing normal files and malicious files into sections. Each section of a normal file is labeled as normal. Each section of a malicious file is labeled as malicious regardless of whether or not the section is malicious. The sections of the normal files and malicious files are used to train the machine learning module. The trained machine learning module is packaged as a machine learning model, which is provided to an endpoint computer. In the endpoint computer, an unknown file is divided into sections, which are input to the machine learning model to identify a malicious section of the unknown file, if any is present in the unknown file.