Abstract: A method and apparatus for starting up a digital currency data processing device, and a digital currency data processing device. The digital currency data processing device includes a hash board including a plurality of hash chip groups. The method includes: transmitting a startup signal to a refrigerating part of a data processing device before turning on a power supply; turning on the power supply; and controlling respective hash chips in each hash chip group to gradually and synchronously turn on cores. The above arrangement improves voltage balance of a hash board, and also ensures the accuracy of a clock signal.

Abstract: Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set which includes a plurality of groups of operating parameters, and-each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameter

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

Abstract: Implementations of the present application propose a method and apparatus for preventing rollback of firmware of a data processing device, and a data processing device. The method includes: enabling a boot loader (BootLoader) to read a current value of a predetermined bit in a one-time programmable memory (eFuse); determining whether the current value and a legal value written into the one-time programmable memory after the latest updating of the firmware of the data processing device satisfy a preset relationship; in response to determining that the current value and the legal value satisfy the preset relationship, enabling the boot loader to call an operating system kernel of the data processing device, and in response to determining that the current value and the legal value do not satisfy the preset relationship, enabling the boot loader not to call the operating system kernel of the data processing device.

Abstract: The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.

Abstract: A control circuit of a large data processing device system for virtual currency and a large data processing device for virtual currency using the control circuit. The control circuit includes: at least two co-controllers (12), each of the co-controllers (12) being in communication connection with one hashboard group (14), to communicate with the connected hashboard group (14) and control operation of the connected hashboard group (14); and a main controller (11) in communication connection with each of the co-controllers (12), to receive and submit tasks and perform, according to the received tasks, coordinated control and task allocation on each of the co-controllers (12), each of the hashboard groups (14) including at least one hashboard.

Abstract: A method and apparatus for starting up a digital currency data processing device, and a digital currency data processing device. The digital currency data processing device includes a hash board including a plurality of hash chip groups. The method includes: transmitting a startup signal to a refrigerating part of a data processing device before turning on a power supply; turning on the power supply; and controlling respective hash chips in each hash chip group to gradually and synchronously turn on cores. The above arrangement improves voltage balance of a hash board, and also ensures the accuracy of a clock signal.

Abstract: Implementations of the present application propose a method and apparatus for preventing rollback of firmware of a data processing device, and a data processing device. The method includes: enabling a boot loader (BootLoader) to read a current value of a predetermined bit in a one-time programmable memory (eFuse); determining whether the current value and a legal value written into the one-time programmable memory after the latest updating of the firmware of the data processing device satisfy a preset relationship; in response to determining that the current value and the legal value satisfy the preset relationship, enabling the boot loader to call an operating system kernel of the data processing device, and in response to determining that the current value and the legal value do not satisfy the preset relationship, enabling the boot loader not to call the operating system kernel of the data processing device.

Abstract: The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device.

Abstract: The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device.

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: Disclosed is a mining machine power adjusting method, including: when a mining machine is in a working stage, collecting an input voltage of the mining machine; adjusting a maximum working power of the mining machine to a first power value by controlling a working frequency and an output voltage of the mining machine when the input voltage is lower than a pre-determined voltage threshold; and adjusting the maximum working power to a second power value by controlling the working frequency and the output voltage of the mining machine when the input voltage is higher than or equal to the voltage threshold, where the first power value is the product of the input voltage multiplied by a rated current of the mining machine, and the second power value is the product of the voltage threshold multiplied by the rated current.