Patents by Inventor Wei-Bin Yang
Wei-Bin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190321238Abstract: A smart diaper sensor, which may be disposed inside a diaper, and may include a sensing element and a wireless RF circuit. The wireless RF circuit may include a transmitter and a wake-up receiver. The wake-up receiver may receive a wake-up signal transmitted from a backend platform to wake up the transmitter. The sensing element may sense the environmental status inside the diaper to generate a sensing signal. The transmitter may receive the sensing signal, and then transmit the sensing signal to the backend platform.Type: ApplicationFiled: October 3, 2018Publication date: October 24, 2019Inventors: HORNG-YUAN SHIH, JEN-SHIUN CHIANG, WEI-BIN YANG, CHI-HSIUNG WANG, YU-CHUAN CHANG, CHENG-WEI YANG
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Patent number: 7656211Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.Type: GrantFiled: December 22, 2006Date of Patent: February 2, 2010Assignee: Industrial Technology Research InstituteInventors: Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo
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Patent number: 7577013Abstract: A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter comprises an input terminal coupled to a write port and an output coupled to a read port. The second inverter comprises an input terminal coupled to the read port and an output terminal coupled to the write port. The third inverter comprises an input terminal coupled to the write port and an output terminal coupled to the read port.Type: GrantFiled: September 23, 2005Date of Patent: August 18, 2009Assignee: Industrial Technology Research InstituteInventor: Wei-Bin Yang
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Patent number: 7557621Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.Type: GrantFiled: September 12, 2007Date of Patent: July 7, 2009Assignee: Industrial Technology Research InstituteInventors: Ting-Sheng Chao, Wei-Bin Yang, Yu-Lung Lo
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Publication number: 20080303562Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.Type: ApplicationFiled: September 12, 2007Publication date: December 11, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Sheng Chao, Wei-Bin Yang, Yu-Lung Lo
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Publication number: 20080106315Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.Type: ApplicationFiled: December 22, 2006Publication date: May 8, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo
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Patent number: 7242231Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di-1 have a fixed phase difference and 1<i<m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f1) according to the set of corresponding clocks, in which f1=A/B f0, A<B and A and B are positive integers.Type: GrantFiled: September 23, 2005Date of Patent: July 10, 2007Assignee: Industrial Technology Research InstituteInventors: Shu-Chang Kuo, Wei-Bin Yang, Kuo-Hsing Cheng
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Publication number: 20060290392Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di?1 have a fixed phase difference and 1<i<m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f1) according to the set of corresponding clocks, in which f ? ? ? 1 = A B ? f ? ? ? 0 , A>B and A and B are positive integers.Type: ApplicationFiled: September 23, 2005Publication date: December 28, 2006Inventors: Shu-chang Kuo, Wei-Bin Yang, Kuo-Hsing Cheng
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Publication number: 20060291320Abstract: A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter comprises an input terminal coupled to a write port and an output coupled to a read port. The second inverter comprises an input terminal coupled to the read port and an output terminal coupled to the write port. The third inverter comprises an input terminal coupled to the write port and an output terminal coupled to the read port.Type: ApplicationFiled: September 23, 2005Publication date: December 28, 2006Inventor: Wei-Bin Yang
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Publication number: 20060143260Abstract: A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to generate an enabling signal and a plurality of control signals, wherein the control signals are used for determining whether to process partial product calculations or not; a selector for generating partial products according to the encoding results from the first encoder and the multiplicand; an adder array, which is composed of a plurality of adders for summing up the partial products. The adder includes a first multiplexer and a second multiplexer. When an adder of one row is disabled by the enabling signal, the first multiplexer receives a summation of the former row and the second multiplexer receives the carry bit of the former row. The multiplier further includes a plurality of third multiplexers for outputting the summation of the adder array.Type: ApplicationFiled: August 24, 2005Publication date: June 29, 2006Inventors: Chuan-Cheng Peng, Wei-Bin Yang