Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: An immersion cooling system is provided. It includes a pressure seal tank, an electronic module, a blower, and a distributor plate. The pressure seal tank contains a cooling liquid, and a gas outlet is disposed on the top or a sidewall of the pressure seal tank, a gas inlet is disposed on the bottom of the pressure seal tank. The gas outlet is higher than the liquid level of the cooling liquid. The electronic module is disposed in the pressure seal tank and immersed in the cooling liquid. The blower is communicated with the pressure seal tank and configured to extract the gas from the gas outlet and inject the gas into the pressure seal tank via the gas inlet. The distributor plate is disposed in the pressure seal tank and located between the electronic module and the gas inlet.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.

Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.

Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The waste collection device includes a fluid ejection element, and the flow out of the fluid ejection element flows toward a space where waste is collected.

Abstract: Provided is a method for skin conditioning comprising administering to a subject in need thereof a composition comprising a Dan Feng peony extract, where the Dan Feng peony extract is extracted from flowers of Dan Feng peony. The Dan Feng peony extract is used to increase the production of hyaluronic acid, maintain the structure of skin keratinocytes, and regulate the moisture content of skin cells.

Abstract: A working fluid recovery device includes an air moving unit, a water removal unit, a working fluid recovery unit, a condenser, and a working fluid collection tank. The air moving unit is configured to suck in a mixed gas including a non-condensable gas, a steam and a vapor phase of working fluid. The water removal unit is connected to the air moving unit, and configured to remove the steam. The working fluid recovery unit is connected to the water removal unit, and configured to recover the vapor phase of the working fluid and exhaust the non-condensable gas. The condenser is connected to the working fluid recovery unit, and configured to condense the vapor phase of the working fluid into a liquid phase of the working fluid. The working fluid collection tank is connected to the condenser, and configured to store the liquid phase of the working fluid.

Abstract: An integrated driving device is provided. The integrated driving device includes a touch sensing circuit and an optical sensing circuit. The touch sensing circuit is configured to perform touch sensing in a plurality of touch sensing periods during a first frame period. The optical sensing circuit is configured to perform optical sensing during at least one optical sensing period during the first frame period to obtain optical sensing signals for generating first ambient light information. The touch sensing periods and the optical sensing period are non-overlapping. Correspondingly, an operation method of an integrated driving device is also provided.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A door lock device is provided and includes: a housing, an acting assembly arranged in the housing and having a lock tongue, an operating assembly arranged in the housing and interlocked with an outdoor handle, and a regulating assembly arranged in the housing for a user to regulate the operating assembly into an interlocking state or an idle state. As such, in the interlocking state, the outdoor handle drives the acting assembly through the operating assembly to cause the lock tongue to extend or retract relative to the housing, and in the idle state, the operating assembly cannot drive the acting assembly and the outdoor handle cannot be interlocked with the lock tongue.