Patents by Inventor Weidong Xiong
Weidong Xiong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162576Abstract: The present disclosure relates to a current collecting component, a battery, and a battery module. The current collecting component includes a current collecting part and a connection part. The current collecting part includes a current collecting region and at least one electrical connection region. The connection part is connected with the current collecting region, wherein a thickness of the current collecting region is greater than a thickness of the electrical connection region.Type: ApplicationFiled: December 20, 2023Publication date: May 16, 2024Applicant: Xiamen Hithium Energy Storage Technology Co., Ltd.Inventors: Yongfeng XIONG, Weidong XU
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Publication number: 20080238477Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: ApplicationFiled: February 25, 2008Publication date: October 2, 2008Applicant: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7342416Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: GrantFiled: November 20, 2006Date of Patent: March 11, 2008Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Publication number: 20070089082Abstract: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.Type: ApplicationFiled: November 8, 2006Publication date: April 19, 2007Applicant: ACTEL CORPORATIONInventors: Tong Liu, Jung-Cheun Lien, Sheng Feng, Eddy Huang, Chung-Yuan Sun, Naihui Liao, Weidong Xiong
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Publication number: 20070075742Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: ApplicationFiled: November 20, 2006Publication date: April 5, 2007Applicant: ACTEL CORPORATIONInventors: Sheng Feng, Jung-Cheun Lien, Eddy Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7157938Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: GrantFiled: January 18, 2006Date of Patent: January 2, 2007Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7137095Abstract: A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.Type: GrantFiled: February 15, 2002Date of Patent: November 14, 2006Assignee: Actel CorporationInventors: Tong Liu, Jung-Cheun Lien, Sheng Feng, Eddy C. Huang, Chung-Yuan Sun, Naihui Liao, Weidong Xiong
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Publication number: 20060114024Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: ApplicationFiled: January 18, 2006Publication date: June 1, 2006Inventors: Sheng Feng, Jung-Cheun Lien, Eddy Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7015719Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: GrantFiled: February 11, 2005Date of Patent: March 21, 2006Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 6888375Abstract: An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column.Type: GrantFiled: April 30, 2003Date of Patent: May 3, 2005Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 6700404Abstract: An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column.Type: GrantFiled: January 30, 2002Date of Patent: March 2, 2004Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Publication number: 20030218479Abstract: An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column.Type: ApplicationFiled: April 30, 2003Publication date: November 27, 2003Applicant: Actel Corporation, a California CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong