Abstract: A method of loading configuration data within an integrated circuit that includes multiple dies is disclosed. The method can include receiving configuration data in encrypted form within a first die of the multiple dies of the integrated circuit and decrypting the configuration data within the first die to generate configuration data in unencrypted form. A portion of the configuration data in unencrypted form can be distributed from the first die to each other die of the multiple dies through an interposer to which each die is attached.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.

Abstract: A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.

Abstract: Method and apparatus for self-checking and self-correcting memory states of a programmable resource is described. Programmable resource of an integrated circuit has a first core and a second core instantiated therein. A first internal configuration port and a second internal configuration port of the integrated circuit are respectively connected to the first core and the second core. The second core is coupled to the first core for monitoring operation of the first core with the second core, and the second core is configured to obtain control responsive to a failure of the first core or the first internal configuration port for a self-correcting mode.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: Methods and apparatus for the protection of memory within an integrated circuit (IC) are provided for various phases of operation of the IC. Various portions of sensitive data may be contained within battery backed random access memory (RAM) (310), which may then be protected using either a passive, or an active, zeroization sequence depending upon the phase of operation of the IC. In an idle state, detection circuit (324) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In a configuration state, detection circuit (402) or (504) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In an operational state, various methods may be employed to detect and counteract the unauthorized access to RAM (310).