Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: The invention relates to a device for testing the precision retaining ability and fatigue life of RV reducer. The device includes a workbench, a mounting bracket base, a upper pressure plate for the mounting bracket, a servo motor, a mounting fixed sleeve, a tested RV reducer, a temperature sensor, an extension arm, a simulated swing arm, two counterweight blocks named the first and second counterweight block, the first displacement sensor, a sensor holder, a sensor protector, a detection rod, and the second displacement sensor. The device is equipped with two counterweight blocks at the end of the simulated swing arm to simultaneously provide variable loaded torque and loaded bending moment to the RV reducer. The first displacement sensor is placed under the counterweight block to measure the positioning accuracy and repeat positioning accuracy of RV reducer. The second displacement sensor is placed under the detection rod to measure the bending stiffness of RV reducer.

Abstract: A neural network mapping method and a neural network mapping apparatus are provided. The method includes: mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of a chip; acquiring the number of phases needed by a plurality of processing elements in the chip for completing the calculation tasks, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, mapping the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the first stage of balancing.

Abstract: A neural network mapping method and a neural network mapping apparatus are provided. The method includes: mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of a chip; acquiring the number of Phases needed by a plurality of processing elements in the chip for completing the calculation tasks, and performing a first stage of balancing on the number of Phases of the plurality of processing elements; and based on the number of the Phases of the plurality of processing elements obtained after the first stage of balancing, mapping the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the first stage of balancing.