Patents by Inventor Weihuang Wang

Weihuang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960413
    Abstract: A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 16, 2024
    Assignee: Google LLC
    Inventors: Weihuang Wang, Prashant Chandra
  • Publication number: 20240121320
    Abstract: Aspects of the disclosure are directed to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, scheduling queue, and quality of service arbiter to support scheduling a large number of connections at a high rate.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Abhishek Agarwal, Weihuang Wang, Weiwei Jiang, Srinivas Vaduvatha, Jiazhen Zheng
  • Publication number: 20240111667
    Abstract: Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.
    Type: Application
    Filed: September 28, 2022
    Publication date: April 4, 2024
    Inventors: Abhishek Agarwal, Srinivas Vaduvatha, Weiwei Jiang, Hugh McEvoy Walsh, Weihuang Wang, Jiazhen Zheng, Ajay Venkatesan
  • Patent number: 11943142
    Abstract: Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (SRAMs) and ternary content addressable memories (TCAMs) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of SRAM pools for lookup and a spillover TCAM pool for unresolved hash conflicts.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 26, 2024
    Assignee: MARVELL ASIA PTE, LTD
    Inventors: Jeffrey T. Huynh, Weihuang Wang, Tsahi Daniel, Srinath Atluri, Mohan Balan
  • Patent number: 11914647
    Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Google LLC
    Inventors: Weiwei Jiang, Srinivas Vaduvatha, Prashant R. Chandra, Jiazhen Zheng, Hugh McEvoy Walsh, Weihuang Wang, Abhishek Agarwal
  • Publication number: 20240064215
    Abstract: Compressing connection state information for a network connection including receiving an input bitmap having a sequence of bits describing transmit states and receive states; partitioning the input bitmap into a plurality of equal size blocks; partitioning each of the blocks into a plurality of equal sized sectors; generating a block valid sequence indicating the blocks having at least one bit set; generating, for each block having at least one bit set, a sector information sequence, the sector information sequence indicating, for the corresponding block, the sectors that have at least one bit set and an encoding type for each sector; and generating one or more symbols by encoding each sector that has at least one bit set.
    Type: Application
    Filed: May 22, 2023
    Publication date: February 22, 2024
    Inventors: Srinivas Vaduvatha, Weiwei Jiang, Prashant Chandra, Opeoluwa Oladipo, Jiazhen Zheng, Hugh McEvoy Walsh, Weihuang Wang, Abhishek Agarwal
  • Publication number: 20240063800
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Atluri, Weinan Ma, Shrikant Sundaram Lnu
  • Publication number: 20240048277
    Abstract: The technology is directed to the use of a bitmap generated at a receiver to track the status of received packets sent by a transmitter. The technology may include a network device including an input port, output port, and circuitry. The circuitry may generate a transmitter bitmap that tracks each data packet sent to another network device. The circuitry of the network device may receive, from the other network device, a receiver bitmap that identifies each data packet that is received and not received from the network device. The circuitry may then determine which data packets to retransmit by comparing the transmitter bitmap to the receiver bitmap.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventors: Yuliang Li, Hassan Mohamed Gamal Hassan Wassel, Behnam Montazeri, Weihuang Wang, Srinivas Vaduvatha, Nandita Dukkipati, Prashant R. Chandra, Masoud Moshref Javadi
  • Publication number: 20240045800
    Abstract: Aspects of the disclosure are directed to high performance connection cache eviction for reliable transport protocols in data center networking. Connection priorities for connection entries are determined to store the connection entries in a cache based on their connection priority. During cache eviction, the connection entries with a lowest connection priority are evicted from the cache. Cache eviction can be achieved with low latency at a high rate.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Abhishek Agarwal, Jiazhen Zheng, Srinivas Vaduvatha, Weihuang Wang, Hugh McEvoy Walsh, Weiwei Jiang, Ajay Venkatesan, Prashant R. Chandra
  • Patent number: 11870466
    Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 9, 2024
    Assignee: Marvell Asia PTE, LTD.
    Inventors: Premshanth Theivendran, Weihuang Wang, Sowmya Hotha, Srinath Atluri
  • Publication number: 20230421657
    Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventors: Weihuang Wang, Prashant Chandra, Srinivas Vaduvatha
  • Patent number: 11843378
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: December 12, 2023
    Assignee: Marvel Asia PTE., LTD.
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Atluri, Weinan Ma, Shrikant Sundaram Lnu
  • Publication number: 20230394082
    Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Weiwei Jiang, Srinivas Vaduvatha, Prashant R. Chandra, Jiazhen Zheng, Hugh McEvoy Walsh, Weihuang Wang, Abhishek Agarwal
  • Publication number: 20230393987
    Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Jiazhen Zheng, Srinivas Vaduvatha, Hugh McEvoy Walsh, Prashant R. Chandra, Abhishek Agarwal, Weihuang Wang, Weiwei Jiang
  • Patent number: 11824954
    Abstract: A communication protocol system is provided for reliable transport of packets. Transport of packets includes transmitting, by a sender entity over a connection to a receiver entity, a plurality of packets in a first order, maintaining, by the sender entity, one or more sliding windows including a plurality of bits, wherein each bit of the sliding window represents a respective packet of the plurality of packets, receiving, by the sender entity, one or more acknowledgments indicating that one or more of the plurality of packets have been received by the receiver entity, each of the acknowledgments referencing a respective packet of the plurality of packets and modifying, by the sender entity, values of one or more of the plurality of bits in the sliding window corresponding to the one or more acknowledgments received.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: November 21, 2023
    Assignee: Google LLC
    Inventors: Weihuang Wang, Prashant R. Chandra, Srinivas Vaduvatha
  • Publication number: 20230362098
    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventors: Xiaoming Wang, Prashant Chandra, Neelesh Bansod, Nandita Dukkipati, Hassan Wassel, Gautam Kumar, Weihuang Wang, Michael Marty, Nicholas McDonald
  • Patent number: 11711311
    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 25, 2023
    Assignee: Google LLC
    Inventors: Xiaoming Wang, Prashant Chandra, Neelesh Bansod, Nandita Dukkipati, Hassan Wassel, Gautam Kumar, Weihuang Wang, Michael Marty, Nicholas McDonald
  • Publication number: 20230216797
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Application
    Filed: March 3, 2023
    Publication date: July 6, 2023
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20230205708
    Abstract: A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Weihuang Wang, Prashant Chandra
  • Patent number: 11627087
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 11, 2023
    Assignee: MARVELL ASIA PTE, LTD
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava