Patents by Inventor Weimin Zeng
Weimin Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096680Abstract: An electrostatic chuck including a clamping layer having a first clamping electrode and a second clamping electrode is disclosed. A first clamping electrode defining a first clamping zone and a second clamping zone is provided. The first clamping zone and the second clamping zone are separated by a first gap and are electrically connected by at least one electrical connection extending across the first gap. A second clamping electrode disposed radially outward from the first clamping electrode. The second clamping electrode defining a third clamping zone and a fourth clamping zone that are separated by a second gap. The third clamping zone and the fourth clamping zone are electrically connected by at least one electrical connection extending across the second gap. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Maolin Long, Weimin Zeng
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Patent number: 11837493Abstract: An electrostatic chuck including a clamping layer having a first clamping electrode and a second clamping electrode is disclosed. A first clamping electrode defining a first clamping zone and a second clamping zone is provided. The first clamping zone and the second clamping zone are separated by a first gap and are electrically connected by at least one electrical connection extending across the first gap. A second clamping electrode disposed radially outward from the first clamping electrode. The second clamping electrode defining a third clamping zone and a fourth clamping zone that are separated by a second gap. The third clamping zone and the fourth clamping zone are electrically connected by at least one electrical connection extending across the second gap. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided.Type: GrantFiled: April 11, 2022Date of Patent: December 5, 2023Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.Inventors: Maolin Long, Weimin Zeng
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Publication number: 20230308687Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Applicant: Realtek Semiconductor Corp.Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
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Patent number: 11770524Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.Type: GrantFiled: November 11, 2021Date of Patent: September 26, 2023Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
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Patent number: 11750800Abstract: A prediction circuit in an encoder utilizes a specific partition mode to process a super block for generating a plurality of reconstructed pixel values for each block in the super block, and the reconstructed pixel values of each block are directly utilized as reference pixels for other blocks to perform intra-frame prediction, so as to improve the efficiency of the encoder.Type: GrantFiled: May 30, 2022Date of Patent: September 5, 2023Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Jing Wang, Wei Li
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Publication number: 20230141735Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.Type: ApplicationFiled: November 11, 2021Publication date: May 11, 2023Applicant: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
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Publication number: 20230005778Abstract: An electrostatic chuck including a clamping layer having a first clamping electrode and a second clamping electrode is disclosed. A first clamping electrode defining a first clamping zone and a second clamping zone is provided. The first clamping zone and the second clamping zone are separated by a first gap and are electrically connected by at least one electrical connection extending across the first gap. A second clamping electrode disposed radially outward from the first clamping electrode. The second clamping electrode defining a third clamping zone and a fourth clamping zone that are separated by a second gap. The third clamping zone and the fourth clamping zone are electrically connected by at least one electrical connection extending across the second gap. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided.Type: ApplicationFiled: April 11, 2022Publication date: January 5, 2023Inventors: Maolin Long, Weimin Zeng
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Publication number: 20220415619Abstract: A plasma processing apparatus including a processing chamber having one or more sidewalls and a dome is provided. The plasma processing apparatus includes a workpiece support disposed in the processing chamber configured to support a workpiece during processing, an induction coil assembly for producing a plasma in the processing chamber, a Faraday shield disposed between the induction coil assembly and the dome, the Faraday shield comprising an inner portion and an outer portion, and a thermal management system. The thermal management system including one or more heating elements configured to heat the dome, and one or more thermal pads disposed between an outer surface of the dome and the heating elements, wherein the one or more thermal pads are configured to facilitate heat transfer between the one or more heating elements and the dome. Thermal management systems and methods for processing workpieces are also provided.Type: ApplicationFiled: May 23, 2022Publication date: December 29, 2022Inventors: Maolin Long, Weimin Zeng, Yu Guan
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Patent number: 11523117Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.Type: GrantFiled: March 22, 2021Date of Patent: December 6, 2022Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
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Patent number: 11494869Abstract: The present application provides a method for storing an image frame in a memory, including: receiving the image frame; dividing the image frame into M rows of data block rows along a first direction; dividing each of the M rows of data block rows into N data blocks along a second direction perpendicular to the first direction; performing a compression operation upon each of the M*N data blocks individually to generate M*N compressed data blocks; and storing N compressed data blocks corresponding to the 1st data block row of the M data block rows and N compressed data blocks corresponding to the (P+1)th data block row of the M data block rows in a continuous storage space in the memory, wherein M, N, and P are integers, and M>1, N>0 and P<M.Type: GrantFiled: September 30, 2020Date of Patent: November 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Weimin Zeng, Jeng-Shiou Lai
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Publication number: 20220330955Abstract: A guide plate for spine surgery incl odes a guide plate body. The guide plate body includes a medial surface matching the back surface of surgical segment centrum. The guide plate body is provided with a guide hole. The outer surface of guide block is conical, the guide plate body is provided with a drill hole corresponding to the guide block. The drill hole matches the outer surface of front end of guide block, the guide block is embedded in the drill hole.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Haiming Jin, Xiangyang Wang, Weimin Zeng, Xuyao Han, Yingjing Chen, Sunren Sheng, Naifeng Tian, Sheng Wang
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Publication number: 20220303538Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
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Publication number: 20220208523Abstract: A gas injection assembly for injecting gas into a processing chamber is provided. In some examples, the gas injection assembly can include an inlet for receiving a gas flow. The gas injection assembly can include a plurality of gas feed ports for distributing the gas flow received from the inlet. The gas injection assembly can include a plurality of subchannels vertically arranged inside of the gas injection assembly, including: an upper subchannel for receiving the gas flow from the inlet and subdividing the gas flow into a set of orifices to form a first gas flow branch and a second gas flow branch, the first gas flow branch corresponding to a first portion of the gas flow passing through a first subset of the set of orifices and the second gas flow branch corresponding to a second portion of the gas flow passing through a second subset of the set of orifices; and a plurality of outlet subchannels for subdividing the gas flow into the plurality of gas feed ports.Type: ApplicationFiled: December 9, 2021Publication date: June 30, 2022Inventors: Maolin Long, Weimin Zeng
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Patent number: 11313034Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.Type: GrantFiled: November 16, 2017Date of Patent: April 26, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Huixiong Dai, Khoi Phan, Christopher Ngai, Rongjun Wang, Xianmin Tang
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Publication number: 20220101484Abstract: The present application provides a method for storing an image frame in a memory, including: receiving the image frame; dividing the image frame into M rows of data block rows along a first direction; dividing each of the M rows of data block rows into N data blocks along a second direction perpendicular to the first direction; performing a compression operation upon each of the M*N data blocks individually to generate M*N compressed data blocks; and storing N compressed data blocks corresponding to the 1st data block row of the M data block rows and N compressed data blocks corresponding to the (P+1)th data block row of the M data block rows in a continuous storage space in the memory, wherein M, N, and P are integers, and M>1, N>0 and P<M.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: WEIMIN ZENG, JENG-SHIOU LAI
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Publication number: 20210337192Abstract: An image processing method includes: determining a first block and a second block corresponding to a current block; dividing each of the current block, the first block and the second block into a plurality of clusters; for a cluster having a corresponding location within each of the current block, the first block and the second block, performing gradient calculations on pixel values within the cluster of the first block and pixel values within the cluster of the second block, and accordingly determining an adjustment value, wherein a window size of the cluster used in the gradient calculations is one or zero; and for a pixel within the cluster of the current block, referring to a pixel value of the pixel of the first block, a pixel value of the pixel of the second block and the adjustment value to calculate a pixel value of the pixel of the current block.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Inventors: Weimin Zeng, Chi-Wang Chai, Wujun Chen, Jing Wang, Rong Zhang
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Patent number: 11051013Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.Type: GrantFiled: November 12, 2019Date of Patent: June 29, 2021Assignee: Realtek Semiconductor Corp.Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
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Publication number: 20210144368Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.Type: ApplicationFiled: November 12, 2019Publication date: May 13, 2021Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
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Patent number: 10991579Abstract: The present disclosure generally relates to tin oxide films prepared by physical vapor deposition using a doped tin target. The semiconductor film may include tin and oxygen, and may be formed in a PVD chamber including a silicon doped tin target. Additionally, the semiconductor film may be smooth compared to similarly formed films without a doped target. The semiconductor film may be deposited by applying an electrical bias to a sputtering silicon doped tin target including the silicon in an amount of 0.5 to 5% by atomic weight of the total target. The semiconductor film has a smooth surface morphology compared to similarly formed tin oxide films formed without a doped target.Type: GrantFiled: May 1, 2019Date of Patent: April 27, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Weimin Zeng, Yong Cao
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Patent number: 10972767Abstract: A transmitter for handling multiple formats of a video sequence, comprises a preprocessing module, for receiving a first format of a video sequence, to generate metadata of a second format of the video sequence according to the first format of the video sequence and the second format of the video sequence; and an encoder, couple to the preprocessing module, for transmitting the first format of the video sequence and the metadata in a bit stream to a receiver.Type: GrantFiled: October 29, 2018Date of Patent: April 6, 2021Assignee: Realtek Semiconductor Corp.Inventors: Lingzhi Liu, Li Liu, Jing Wang, Wujun Chen, Qingxi He, Wei Pu, Weimin Zeng, Chi-Wang Chai