Patents by Inventor Weiming Guo
Weiming Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097443Abstract: A source-network-load-storage coordination dispatching method in a background of a coupling of renewable energy sources, including: taking an expectation of a minimum grid operating cost in a dispatching cycle as an objective function; generating an approximate value function of an output of a set for generating electricity from renewable energy sources and a user load, and constructing a source-network-load-storage coordination dispatching model with combination of the objective function; obtaining forecast data of the output of a set for generating electricity from renewable energy sources and the user load, and inputting the forecast data into the dispatching model for solving; performing iterative updating on the approximate value function, importing the approximate value function after the iterative updating into the dispatching model for iterative solving, and terminating an iterative process until a solving result satisfies a preset convergence condition; and using a solving result of a last iterationType: ApplicationFiled: January 14, 2022Publication date: March 21, 2024Inventors: Feng Guo, Jian Yang, Lintong Wang, Jiahao Zhou, Yefeng Luo, Dongbo Zhang, Yuande Zheng, Guode Ying, Minzhi Chen, Xinjian Chen, Jie Yu, Weiming Lu, Chi Zhang, Yizhi Zhu, Binren Wang, Chenghuai Hong
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Patent number: 10818491Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.Type: GrantFiled: May 28, 2019Date of Patent: October 27, 2020Assignee: IMEC vzwInventors: Ming Zhao, Weiming Guo
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Patent number: 10566250Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: GrantFiled: February 8, 2019Date of Patent: February 18, 2020Assignee: IMEC vzwInventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Publication number: 20190362967Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.Type: ApplicationFiled: May 28, 2019Publication date: November 28, 2019Inventors: Ming Zhao, Weiming Guo
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Publication number: 20190244862Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: ApplicationFiled: February 8, 2019Publication date: August 8, 2019Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Patent number: 10224250Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: GrantFiled: September 22, 2017Date of Patent: March 5, 2019Assignee: IMEC vzwInventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Publication number: 20180082901Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: ApplicationFiled: September 22, 2017Publication date: March 22, 2018Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Patent number: 9708224Abstract: The invention proposed a novel hot pressing flowing sintering method to fabricate textured ceramics. The perfectly 2-dimensional textured Si3N4 ceramics (Lotgering orientation factor fL 0.9975) were fabricated by this method. During the initial sintering stage, the specimen flowed along the plane which is perpendicular to the hot pressing direction under pressure, through the controlling of the graphite die movement. The rod-like ?-Si3N4 nuclei was easily to texture during the flowing process, due to the small size of the ?-Si3N4 nuclei and the high porosity of the flowing specimen. After aligned, the ?-Si3N4 grains grew along the materials flowing direction with little constraint. textured Si3N4 ceramics fabricated by this invention also showed high aspect ratio. Compared to the conventional hot-forging technique which contained the sintering and forging processes, hot pressing flowing sintering proposed is simpler and lower cost to fabricate textured Si3N4.Type: GrantFiled: August 10, 2015Date of Patent: July 18, 2017Assignees: DONGGUAN SOUTH CHINA DESIGN AND INNOVATION INST., GUANGDONG UNIVERSITY OF TECHNOLOGYInventors: Shanghua Wu, Qiangguo Jiang, Weiming Guo, Shangxian Gu, Maopeng Zhou, Wei Liu, Lixia Cheng, Bo Wang, Chengyong Wang, Qimin Wang
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Publication number: 20170015593Abstract: The invention proposed a novel hot pressing flowing sintering method to fabricate textured ceramics. The perfectly 2-dimensional textured Si3N4 ceramics (Lotgering orientation factor fL 0.9975) were fabricated by this method. During the initial sintering stage, the specimen flowed along the plane which is perpendicular to the hot pressing direction under pressure, through the controlling of the graphite die movement. The rod-like ?-Si3N4 nuclei was easily to texture during the flowing process, due to the small size of the ?-Si3N4 nuclei and the high porosity of the flowing specimen. After aligned, the ?-Si3N4 grains grew along the materials flowing direction with little constraint. textured Si3N4 ceramics fabricated by this invention also showed high aspect ratio. Compared to the conventional hot-forging technique which contained the sintering and forging processes, hot pressing flowing sintering proposed is simpler and lower cost to fabricate textured Si3N4.Type: ApplicationFiled: August 10, 2015Publication date: January 19, 2017Inventors: Shanghua Wu, Qiangguo Jiang, Weiming Guo, Shangxian Gu, Maopeng Zhou, Wei Liu, Lixia Cheng, Bo Wang, Chengyong Wang, Qimin Wang