Patents by Inventor Wei-Ming Lin

Wei-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002684
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 12000455
    Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Chen Ho, Chih Ping Liao, Chien Ting Lin, Jie-Ying Yang, Wei-Ming Wang, Ker-Hsun Liao, Chi-Hsun Lin
  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Publication number: 20240153901
    Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 9, 2024
    Inventors: Yu-Hung Lin, Han-Jong Chia, Wei-Ming Wang, Kuo-Chung Yee, Chen Chen, Shih-Peng Tai
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240138098
    Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Yu-Ming Lin
  • Patent number: 11968800
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Sheng-Yan Chen
  • Publication number: 20240128178
    Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Patent number: 11944935
    Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Tsung-I Lin
  • Patent number: 11944412
    Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
  • Publication number: 20240107731
    Abstract: The present disclosure provides a matte-type electromagnetic interference shielding film including bio-based components, which includes a bio-based insulating layer, a bio-based adhesive layer, a metal layer, and a bio-based electrically conductive adhesive layer. The matte-type electromagnetic interference shielding film including the bio-based component of the present disclosure has a matte appearance and high bio-based content and has the advantages of good surface insulation, high surface hardness, good chemical resistance, high shielding performance, good adhesion strength, low transmission loss, high transmission quality, good operability, high heat resistance, and the inner electrically conductive adhesive layer with long shelf life and storage life. The present disclosure further provides a preparation method thereof.
    Type: Application
    Filed: July 14, 2023
    Publication date: March 28, 2024
    Inventors: Bo-Sian DU, Wei-Chih LEE, Chia-Hua HO, Chih-Ming LIN, Chien-Hui LEE
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Patent number: 11934065
    Abstract: A display device includes a substrate, a first light emitting element, a second light emitting element, and an optical film sheet. The first light emitting element and the second light emitting element are disposed on the substrate. The first light emitting element emits a first light, and the first light has a first wavelength range. The second light emitting element emits a second light, and the second light has a second wavelength range. The optical film sheet is disposed above the first light emitting element and the second light emitting element. The optical film sheet includes a first zone and a second zone. The first zone includes a first cholesteric liquid crystal, and the first cholesteric liquid crystal reflects light in at least the first wavelength range. The second zone includes a second cholesteric liquid crystal, and the second cholesteric liquid crystal reflects light in at least the second wavelength range.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: March 19, 2024
    Assignee: AUO Corporation
    Inventors: Wan Heng Chang, Min-Hsuan Chiu, Syuan-Ying Lin, Wei-Ming Cheng
  • Patent number: 11935825
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
  • Publication number: 20240089090
    Abstract: A method for managing a digital identity system includes generating a user digital identity for a user, generating an asset digital identity for an asset, generating a user public key and a user private key after the user digital identity is generated, generating descriptive data related to the asset, generating a data public key and a data private key after the descriptive data is generated, encrypting the data with the data public key to generate encrypted data, saving the data private key on a user end, uploading the encrypted data to a cloud database, a platform reading the encrypted data from the cloud database, a data requester querying and requesting for data, forwarding a data request to a data owner in an qualified data owner set and granting a data access to the data request if the data owner accepts the data request.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 14, 2024
    Applicant: LSC Ecosystem Corporation
    Inventors: Wei-Ming Li, Kuan-Hsun Cho, Sung-Ching Lin
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang