Abstract: A method includes generating a first subset of codeword symbols by processing, during each of a plurality of iterations, a first input and a second input. The first input is a function of (i) an output, during a respective one of the plurality of iterations, of a last processing stage of a first plurality of processing stages and (ii) a symbol, of a first subset of original symbols, corresponding to the respective iteration. The second input is a function of (i) an output, during the respective iteration, of a last processing stage of the second plurality of processing stages and (ii) a symbol, of a second subset of original symbols, corresponding to the respective iteration. The method also includes generating a second subset of codeword symbols by processing, during each of the plurality of iterations, the first input and the second input.

Abstract: A first wireless device includes a coding module that encodes packets and adds dummy data to a second packet. A first receiver (i) in response to transmission of a first packet, receives a first acknowledgement (ACK) signal, and (ii) in response to transmission of the second packet, receives a second ACK signal. Reception of the first ACK signal is delayed a first delay period from an end of the transmission of the first packet. Reception of the second ACK signal is delayed a second delay period from an end of the transmission of the dummy data. The coding module, prior to the transmission of the second packet and based on time to process the first and second packets at a second wireless device, determines the amount of dummy data to add to the second packet such that the first delay period is a same length as the second delay period.

Abstract: A network device includes a receiver that receives a first signal on a channel. A demodulator outputs demodulated data based on the first signal. A gain device, based on a change in a gain of the first signal, generates a second signal. A validating device determines whether the first signal is a valid direct sequence spread spectrum signal and based on whether the first signal is a valid direct sequence spread spectrum signal, generates a third signal. An assessment device: determines whether the demodulated data includes a predetermined header, where the predetermined header includes a predetermined sequence; determines whether the channel is busy based on the second signal, the third signal, and whether the demodulated data includes the predetermined header with the predetermined sequence; and generates a channel signal indicating whether the channel is busy. A transmitter, based on the channel signal, transmits a fourth signal on the channel.

Abstract: A method of operating a system on chip. The system on chip includes a controller. The method includes: receiving, at the system on chip and in a storage drive, encrypted content and an encrypted content key; storing the encrypted content and the encrypted content key in a storage device; and transmitting the encrypted content key from the controller to a first decryption module. The method further includes: decrypting the encrypted content key to generate a content key based on an identification of the system on chip; transmitting the encrypted content from the controller to a second decryption module; and decrypting the encrypted content based on the content key to generate content.

Abstract: A circuit includes a multiplexer, a first measurement device, and a decision device. The multiplexer is configured to receive signals from antennas, where the signals include (i) a first signal received from a first antenna of the antennas, and (ii) a second signal received from a second antenna of the antennas. The first measurement device is configured to (i) determine a first peak-to-average ratio based on the first signal, and (ii) determine a second peak-to-average ratio based on the second signal. The decision device is configured to, based on the first peak-to-average ratio and the second peak-to-average ratio, signal the multiplexer to select one of the antennas.

Abstract: An integrated circuit includes a first memory, a second memory, a processor, and a descrambler. The first memory is configured to store a key. The first memory is a one-time-programmable memory. The processor is configured to: determine whether the first memory has been programmed; and in response to the first memory not having been programmed, (i) load firmware from a third memory into the second memory, and (ii) execute the firmware. The third memory is separate from the integrated circuit. The processor is also configured to, in response to the first memory having been programmed, load the firmware from the third memory into the second memory. The descrambler is configured to, in response to the first memory having been programmed, descramble the firmware based on the key.

Abstract: An apparatus for detecting and correcting errors in a received codeword includes a syndrome calculator, error locator polynomial generator, and symbol corrector. The syndrome calculator has a first input to receive a first plurality of symbols, a second input to receive a second plurality of symbols, and a plurality of processing stages each coupled to the first and second inputs. Each processing stage is configured to process a symbol of the first plurality of symbols, and a symbol of the second plurality of symbols, during each of a plurality of iterations to generate a respective syndrome value after the iterations. The syndrome calculator also has a syndrome output configured to output the respective syndrome values. The error locator polynomial generator has a syndrome input coupled to both the syndrome output and an error location output, and the symbol corrector has an error location input coupled to the error location output.

Abstract: A secure storage device includes a storage medium configured to store encrypted digital content and an encrypted content key. A public key decryption module is configured to generate a private key for the secure storage device based on an identification (ID) code of the secure storage device. The public key decryption module decrypts the encrypted content key using the private key to generate a content key. A block decryption module is configured to receive the encrypted digital content and the content key and decrypt the encrypted digital content using the content key to generate decrypted digital content.

Abstract: A system-on-chip includes first and second memories, a descrambler, and logic. The first memory stores firmware. A first portion of the firmware is scrambled and located at a predetermined address in the first memory. The second memory stores boot code for a processor. In response to the processor being booted, the boot code instructs the processor to read the first portion of the firmware from the predetermined address in the first memory. The descrambler is configured to create a descrambled value by descrambling the first portion of the firmware. The logic is configured to, in response to the descrambled value matching a predetermined authorization code, enable a test interface that allows a device external to the system-on-chip to access the processor through the test interface. The logic is further configured to, in response to the descrambled value not matching the predetermined authorization code, disable the test interface.

Abstract: A transceiver including: an antenna configured to a receive a first signal transmitted on a radio frequency channel; and a peak-to-sidelobe ratio determination unit configured to generate a second signal based on a ratio, in which the ratio is based on a peak value and a sidelobe value, and the peak value and the sidelobe value are determined based on a non-correlated version of the first signal. The transceiver further includes a carrier sense unit configured to, based on the second signal, generate a third signal indicating (i) whether the radio frequency channel is busy or (ii) whether the first signal is valid.

Abstract: A first wireless device comprising: a transmitter configured to transmit, in accordance with a first mode of operation or a second mode of operation, a packet to a second wireless device, wherein the packet includes a header portion and a data portion. A maximum time interval for the second station to respond to the packet is as follows: (i) in response to the packet being transmitted to the second device in accordance with the first mode of operation, the second device is to respond to the packet within a predetermined time period, and (ii) in response to the packet being transmitted to the second device in accordance with the second mode of operation, the second device is to respond to the packet in a time greater than the predetermined time period.

Abstract: A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.

Abstract: A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

Abstract: A system includes a receiver, a processor and a decision device. The receiver receives a first signal via a first antenna, and one of the first signal and a second signal via a second antenna. The processor determines: based on the first signal as received at the first antenna, a first signal-to-noise ratio (SNR) and a first signal quality value; and based on the one of the first and second signals as received at the second antenna, a second SNR and a second signal quality value. The decision device selects one of the first and second antennas based on (i) a difference between the first SNR and the second SNR if the first SNR is greater than the second SNR, or (ii) the first signal quality value and the second signal quality value if the difference between the first SNR and the second SNR is less than a predetermined threshold.

Abstract: In an error correcting code encoder apparatus, a first processor generates a first subset of codeword symbols based on original symbols. The first processor includes a first serial input to receive a first subset of the original symbols. A second processor generates a second subset of the codeword symbols based on the original symbols. The second processor includes a second serial input to receive a second subset of the original symbols.

Abstract: A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.

Abstract: A receiver has a plurality of antennas for receiving a signal. The signal includes a data packet. The receiver includes a correlator to correlate a spreading code with a preamble of the data packet. A first processor determines a signal quality value of the signal at each of the plurality of antennas. The signal quality value at each of the plurality of antennas is determined during the correlation of the spreading code with the preamble of the data packet. A decision unit selects a first antenna of the plurality of antennas for reception of the signal based on the signal quality value determined at each of the plurality of antennas.

Abstract: A secure storage device includes a storage medium configured to store encrypted digital content and an encrypted content key. A public key decryption module is configured to generate a private key for the secure storage device based on an identification (ID) code of the secure storage device. The public key decryption module decrypts the encrypted content key using the private key to generate a content key. A block decryption module is configured to receive the encrypted digital content and the content key and decrypt the encrypted digital content using the content key to generate decrypted digital content.

Abstract: A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Abstract: Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first memory to store firmware for the processor; and a second memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to read a portion of the firmware from a predetermined location in the first memory; wherein the test interface is enabled only when the portion of the firmware has a predetermined value.