Patents by Inventor Weizhong Xu
Weizhong Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9805775Abstract: An integrated circuit may include a memory controller that interfaces with memory that operates using a memory clock signal having repeating memory clock cycles. The memory controller may include controller circuitry that receives memory access requests and generates corresponding memory commands using a controller clock signal having repeating controller clock cycles. The controller circuitry may partition each controller clock cycle into time slots that are associated with respective memory clock cycles. Each generated memory command may require a corresponding number of memory clock cycles to fulfill using the memory. The controller circuitry may assign a time slot to each memory command while preventing conflicts with previously issued memory commands.Type: GrantFiled: November 8, 2013Date of Patent: October 31, 2017Assignee: Altera CorporationInventors: Yu Ying Ong, Weizhong Xu
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Patent number: 9342402Abstract: A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.Type: GrantFiled: January 28, 2014Date of Patent: May 17, 2016Assignee: Altera CorporationInventors: Yu Ying Ong, Weizhong Xu
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Patent number: 9330218Abstract: An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.Type: GrantFiled: August 29, 2014Date of Patent: May 3, 2016Assignee: Altera CorporationInventors: Gordon Raymond Chiu, Sean Shau-Tu Lu, Warren Trent Nordyke, Bonnie I. Wang, Weizhong Xu
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Patent number: 8645638Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.Type: GrantFiled: May 7, 2012Date of Patent: February 4, 2014Assignee: NVIDIA CorporationInventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
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Publication number: 20120292673Abstract: A semiconductor device and manufacture method thereof is disclosed. The method includes: forming a gate on a substrate; forming a stack including a first material layer, a second material layer, and a third material layer from inner to outer in sequence; etching the stack to form sidewall spacers on opposite sidewalls of the gate; performing ion implantation to form a source region and a drain region; partially or completely removing the remaining portion of the third material layer; performing a pre-cleaning process, wherein all or a portion of the remaining portion of the second material layer is removed; forming silicide on top of the source region, the drain region, and the gate; depositing a stress film to cover the silicide and the remaining portion of the first material layer. According to the above method, the stress proximity technique (SPT) can be realized while avoiding silicide loss.Type: ApplicationFiled: December 13, 2011Publication date: November 22, 2012Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Weizhong Xu
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Publication number: 20120221808Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.Type: ApplicationFiled: May 7, 2012Publication date: August 30, 2012Applicant: NVIDIA CorporationInventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
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Patent number: 8176265Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.Type: GrantFiled: June 21, 2011Date of Patent: May 8, 2012Assignee: NVIDIA CorporationInventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
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Patent number: 8108625Abstract: Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.Type: GrantFiled: October 30, 2006Date of Patent: January 31, 2012Assignee: NVIDIA CorporationInventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
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Publication number: 20110252204Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Applicant: NVIDIA CorporationInventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
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Patent number: 7880747Abstract: A technique for handling floating-point special values, e.g., Infinity, NaN, ?Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.Type: GrantFiled: December 13, 2006Date of Patent: February 1, 2011Assignee: NVIDIA CorporationInventors: Steven E. Molnar, Jerome F. Duluk, Jr., Henry P. Moreton, Daniel P. Wilde, Mark J. French, Bengt-Olaf Schneider, Jonathan J. Dunaisky, Weizhong Xu