Abstract: A linear guideway, a sliding module thereof, and a circulation seat thereof are provided. The circulation seat has an inherently one-piece structure, which includes two turning portions, a middle retaining portion, and two lateral retaining portions. The middle retaining portion has a two-stepped structure, which includes a connection bar and a limiting bar that is connected to the connection bar. The connection bar is connected to and arranged between the two turning portions, and a distance between two long lateral surfaces of the connection bar gradually increases along a direction away from the limiting bar. The two lateral retaining portions are connected to and arranged between the two turning portions, and the two lateral retaining portions are respectively located at two opposite sides of the middle retaining portion.

Abstract: A linear guideway, a sliding module thereof, and a circulation seat thereof are provided. The circulation seat has an inherently one-piece structure, which includes two turning portions, a middle retaining portion, and two lateral retaining portions. The middle retaining portion has a two-stepped structure, which includes a connection bar and a limiting bar that is connected to the connection bar. The connection bar is connected to and arranged between the two turning portions, and a distance between two long lateral surfaces of the connection bar gradually increases along a direction away from the limiting bar. The two lateral retaining portions are connected to and arranged between the two turning portions, and the two lateral retaining portions are respectively located at two opposite sides of the middle retaining portion.

Abstract: A controller located in a memory device is disclosed. The controller includes a feedback regulation circuit. The feedback regulation circuit is configured to generate a feedback voltage to a power supply circuit according to a power consumption of the controller, for the power supply circuit to adjust an input voltage input to the memory device according to the feedback voltage. When the power consumption of the controller is lower, the feedback voltage is higher, so that the input voltage is lower, and when the power consumption of the controller is higher, the feedback voltage is lower, so that the input voltage is higher.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A power-saving device and method are applicable to a first electronic device having at least one connection interface, and the first electronic device is coupled to a second electronic device via a bus. The power-saving device includes a detection circuit, a power control circuit, and a connection control circuit. The detection circuit is coupled to the connection interface, to detect a load state of the connection interface and generate a detection signal. The power control circuit controls power supplied to the first electronic device via the bus in response to a state of the detection signal. The connection control circuit controls a connection state of the bus according to the detection signal.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein each pattern configuration has at least two different pattern elements allowing other pattern elements be chosen to align when any one of the pattern elements on the substrate was damaged during process.

Abstract: A bank structure for a display panel is provided. The display panel comprises a substrate, and the bank structure is formed on the surface of the substrate. The bank structure comprises a periphery and a partition, wherein the periphery forms a receiving space with the substrate and the partition is disposed in the receiving space for separating the receiving space into two sub-spaces with fluid-communication. Therefore, the ink can be injected and uniformly distributed in the sub-spaces to overcome the disadvantages of poor injection precision and increasing the spray control of the ink.

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and the first and third rectangular regions have the same first pattern configuration having a first pattern element, a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, and the second and fourth rectangular regions have the same second pattern configuration having a second pattern element, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein, the first pattern element is different from the second pattern element for allowing the second pattern configuration be chosen to align when the first pattern configurat

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.

Abstract: An ink composition for producing a color filter is provided. The ink composition comprises a colorant, a binder and plural solvents. A color filter production method using the above-mentioned ink composition is also provided. The ink composition is adhered to the designated light transmitting regions on the surface of a transparent substrate. Then, the ink composition adhered to the designated light transmitting regions is solidified.

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and the first and third rectangular regions have the same first pattern configuration having a first pattern element, a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, and the second and fourth rectangular regions have the same second pattern configuration having a second pattern element, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein, the first pattern element is different from the second pattern element for allowing the second pattern configuration be chosen to align when the first pattern configurat

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein each pattern configuration has at least two different pattern elements allowing other pattern elements be chosen to align when any one of the pattern elements on the substrate was damaged during process.