Abstract: A clock data recovery circuit and a clock data recovery method are provided. The clock data recovery circuit includes a time delay loop (100), a frequency locking loop (200) and a deserializer (300). The time delay loop (100) is configured to delay input data according to a phase of a clock signal to realize phase alignment; the frequency locking loop (200) is connected to the time delay loop (100), and is configured to adjust a frequency of the clock signal according to the delayed input data to make the frequency of the clock signal be consistent with a frequency of the input data; and the deserializer (300) is respectively connected to the time delay loop (100) and the frequency locking loop (200), and is configured to deserialize the input data according to the clock signal.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.

Abstract: An exemplary embodiment of the present invention provides an optical communication system. The optical communication system can comprise a self-powered sensor and an optical array. The self-powered sensor can be configured to receive a mechanical input and generate an electrical signal corresponding to the mechanical input. The optical array can be configured to receive the electrical signal and generate an optical output. The optical output can correspond to the mechanical input.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: An exemplary embodiment of the present invention provides an optical communication system. The optical communication system can comprise a self-powered sensor and an optical array. The self-powered sensor can be configured to receive a mechanical input and generate an electrical signal corresponding to the mechanical input. The optical array can be configured to receive the electrical signal and generate an optical output. The optical output can correspond to the mechanical input.

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.