Patents by Inventor Wen-Chih Chiu
Wen-Chih Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170339Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.Type: ApplicationFiled: March 2, 2023Publication date: May 23, 2024Inventors: Te-Chih Hsiung, Yun-Hua Chen, Yang-Cheng Wu, Sheng-Hsun Fu, Wen-Kuo Hsieh, Chih-Yuan Ting, Huan-Just Lin, Bing-Sian Wu, Yi-Hsuan Chiu
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Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
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Publication number: 20240107414Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
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Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
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Patent number: 8158456Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.Type: GrantFiled: December 5, 2008Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Fa Chen, Chen-Shien Chen, Wen-Chih Chiu
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Patent number: 7986416Abstract: A size and position detecting system includes a laser sensor and a controller. The laser sensor includes an emitter emitting a laser beam to a receiver. The controller is configured to compute a first time of how long the emitter emits the laser beam and a second time of how long the receiver receives the laser beam when a cutting tool moves along a first direction perpendicular to and coplanar with a straight line connecting the emitter and the receiver. The controller is configured to record a first position of the cutting tool at a moment when the second time is less than the first time, and a second position of the cutting tool when the second time remains changeless for a predetermined amount of time, to determine whether the cutting tool is off-centered according coordinates difference between the first and second positions along the first direction.Type: GrantFiled: April 2, 2009Date of Patent: July 26, 2011Assignee: Foxnum Technology Co., Ltd.Inventor: Wen-Chih Chiu
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Publication number: 20100183388Abstract: A size and position detecting system includes a laser sensor and a controller. The laser sensor includes an emitter emitting a laser beam to a receiver. The controller is configured to compute a first time of how long the emitter emits the laser beam and a second time of how long the receiver receives the laser beam when a cutting tool moves along a first direction perpendicular to and coplanar with a straight line connecting the emitter and the receiver. The controller is configured to record a first position of the cutting tool at a moment when the second time is less than the first time, and a second position of the cutting tool when the second time remains changeless for a predetermined amount of time, to determine whether the cutting tool is off-centered according coordinates difference between the first and second positions along the first direction.Type: ApplicationFiled: April 2, 2009Publication date: July 22, 2010Applicant: FOXNUM TECHNOLOGY CO., LTD.Inventor: Wen-Chih Chiu
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Publication number: 20100144094Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.Type: ApplicationFiled: December 5, 2008Publication date: June 10, 2010Inventors: Ming-Fa Chen, Chen-Shien Chen, Wen-Chih Chiu
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Publication number: 20090241093Abstract: The present invention relates to a method for debugging a programmable logic controller. An invariant logic formula is set up. A program is checked by the invariant logic formula, and if the program satisfies the invariant logic formula, debugging is complete and the process returns to the program checking step. If the program does not satisfy the invariant logic formula, checking is stopped and a warning signal and position or timing of the program error are issued.Type: ApplicationFiled: August 21, 2008Publication date: September 24, 2009Applicant: FOXNUM TECHNOLOGY CO., LTD.Inventors: WEN-CHIH CHIU, CHAU-LIN CHANG, JHY-HAU CHIU
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Publication number: 20090179370Abstract: A workpiece shifting prevention device includes a platform, which is configured for supporting a workpiece thereon; a sensor group mounted in the platform, which is configured for measuring pressures at different points on the platform and converting the pressures into voltage signals; an amplifier group connected to the sensor group, which is configured for amplifying the voltage signals output from the sensor group; and a single chip connected to the amplifier group, which is configured for receiving and processing the amplified voltage signals. The single chip checks if the voltage signals output from the sensor group are equal, and if not, adjusting machining parameters of an implement connected thereto.Type: ApplicationFiled: April 10, 2008Publication date: July 16, 2009Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHING-CHENG YANG, WEN-CHIH CHIU, SHOU-MING LIANG, YAW-SHEN LAI
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Publication number: 20070022222Abstract: A memory device and an associated operating method are provided to implement a customized function of the memory device by using a specially designed command packet. In one embodiment, a manufacture reserved command defined by a standard protocol is used and a corresponding customized command argument is configured, so as to generate a customized command packet compatible with the standard protocol. In another embodiment, an access command defined by the standard protocol is used and an access address, which is either an illegal address or an address lying outside an addressing range of the user area of the memory device, is configured in a corresponding command argument, so as to generate an access command packet. The memory device can perform the customized function according to the customized command packet or the access command packet mention above.Type: ApplicationFiled: July 18, 2006Publication date: January 25, 2007Inventors: Tsung Hsien Wu, Wei Lun Hsu, Wen Chih Chiu, Feng Hsi Lin