Abstract: The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size Si to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: A system and method for maskless direct write lithography are disclosed. The method includes receiving a plurality of pixels that represent an integrated circuit (IC) layout; identifying a first subset of the pixels that are suitable for a first compression method; and identifying a second subset of the pixels that are suitable for a second compression method. The method further includes compressing the first and second subset using the first and second compression method respectively, resulting in compressed data. The method further includes delivering the compressed data to a maskless direct writer for manufacturing a substrate. In embodiments, the first compression method uses a run-length encoding and the second compression method uses a dictionary-based encoding. Due to the hybrid compression method, the compressed data can be decompressed with a data rate expansion ratio sufficient for high-volume IC manufacturing.

Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

Abstract: The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure.

Abstract: A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.

Abstract: Disclosed is a lithography system. The lithography system includes a radiation source to provide radiation energy for lithography exposure; a substrate stage configured to secure a substrate; an imaging lens module configured to direct the radiation energy onto the substrate; at least one sensor configured to detect a radiation signal directed from the substrate; and a pattern extraction module coupled with the at least one sensor and designed to extract a pattern of the substrate based on the radiation signal.

Abstract: A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.

Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.