Abstract: A transmission component with a functional structure has a linear or crossed shaft body, a transmission structure integrally formed on the shaft body and extending in a radial direction; a sensor matching structure and a shaft matching structure formed on the shaft body so that a sensor and a bearing may be conveniently assembled on the shaft body and the size of the transmission component can be miniaturized, and a reinforcing rod which may be inserted into the shaft body in an axial direction to enhance the structure intensity of the shaft body.

Abstract: The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded memory address of the memory address decoder, first and second ports of the dual-port memory are connected to input and output of the bus tri-state buffer respectively, and an output of the arbitration circuit is connected to an enable terminal of the bus tri-state buffer.

Abstract: The present invention discloses a processor capable of alerting its life expectancy and its method. The processor is installed in an electronic device having a control circuit, a frequency divider circuit and a time counter. The control circuit is connected to the frequency divider circuit and the time counter. The frequency divider circuit receives a plurality of high frequencies from the control circuit and converts the high frequencies into a time unit. The time counter adds the time units one by one to obtain a use time. If the use time has reached a predetermined use time, the control circuit will issue a warning to indicate that the life expectancy of the processor is reached, so as to reflect the actual use time of the processor, prevent a change of use time by software, and allow users to timely take proper preventive measures before the processor exceeds its life cycle.

Abstract: The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded memory address of the memory address decoder, first and second ports of the dual-port memory are connected to input and output of the bus tri-state buffer respectively, and an output of the arbitration circuit is connected to an enable terminal of the bus tri-state buffer.

Abstract: The present invention discloses a processor capable of alerting its life expectancy and its method. The processor is installed in an electronic device having a control circuit, a frequency divider circuit and a time counter. The control circuit is connected to the frequency divider circuit and the time counter. The frequency divider circuit receives a plurality of high frequencies from the control circuit and converts the high frequencies into a time unit. The time counter adds the time units one by one to obtain a use time. If the use time has reached a predetermined use time, the control circuit will issue a warning to indicate that the life expectancy of the processor is reached, so as to reflect the actual use time of the processor, prevent a change of use time by software, and allow users to timely take proper preventive measures before the processor exceeds its life cycle.

Abstract: A drive circuit for displaying the partition symbol intermittently comprising at least a pair of buffers, a plurality of display units of seven-segment, a partition symbol display buffer, a control circuit, a display unit of partition symbol, is provided. The pair of buffers store a set of signals. Each of the plurality of display units of seven-segment includes a first display portion and a second display portion, and, responsive to the set of signals, the first display portion and the second display portion are enabled to display. The partition symbol display buffer has an output value. The control circuit resets and sets the partition symbol display buffer in accordance with a predetermined manner. The display unit of partition symbol, in response to the output value, displays the partition symbol intermittently.