Abstract: A computer, including a processor and a memory, the memory including instructions to be executed by the processor to calibrate utility functions that determine optimal vehicle actions based on an approximate Nash equilibrium solution for multiple agents by determining a difference between model-predicted future states for the multiple agents to observed states for the multiple agents. The instructions can include further instructions to determine a vehicle path for a vehicle based on the optimal vehicle actions.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: Disclosed herein are hydrogel compositions comprising a triblock copolymer having a formula A-B-A, wherein A is a polycaprolactone (PCL) block or a polyvalerolactone (PVL) block and B is a polyethylene glycol (PEG) block. Also disclosed are methods of making a hydrogel comprising providing a photoinitiator and a triblock copolymer having a formula A-B-A, wherein the triblock copolymer comprises one or more ethylenically unsaturated moieties; and photocrosslinking the triblock copolymer, thereby forming a hydrogel.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: Disclosed are a method and apparatus for accelerating inference of a neural network model, an electronic device, and a medium. The method includes: acquiring image training data, text training data, or speech training data; determining a first neural network model to be accelerated; converting a preset operation on a preset network layer in the first neural network model to a first operation for simulating operational logic of a target operation to obtain a second neural network model; performing, based on the image training data, the text training data, or the speech training data, quantization aware training on the second neural network model by a preset bit width to obtain a third neural network model which is quantized; and converting the first operation of the third neural network model to the target operation, to obtain a target neural network model, which is accelerated, corresponding to the first neural network model.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: The present disclosure provides a method and an apparatus for information transmission, the method including: transmitting a Physical Random Access Channel (PRACH) or a Physical Uplink Shared Channel (PUSCH) over an uplink narrow band to a wireless communication node, wherein the uplink narrow band is selected from a set of narrow bands based on a coverage level of each narrow band in the set of narrow bands; and receiving a downlink control channel or a Physical Downlink Shared Channel (PDSCH) over a downlink narrow band corresponding to the uplink narrow band or an anchor carrier, wherein the set of narrow bands is configured by the wireless communication node.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: Methods and systems are provided for an engine for adjusting cylinder parameter settings to optimize engine output during a transient mode. In one example, a method may include adjusting cylinder parameter settings, including a cam timing setting, a spark timing setting, and a fuel injection timing setting based on a chamber temperature in response to a rate of fuel injection acceleration being greater than a positive threshold, thus indicating the engine is in the transient mode.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

Abstract: A display apparatus includes a driving backplane and a light-emitting element. The driving backplane includes a substrate, a pixel driving circuit disposed on the substrate and a pad electrically connected to the pixel driving circuit. The pad has a first metal layer, a first intermetallic layer and a first diffusion barrier layer, wherein the first metal layer, the first intermetallic layer and the first diffusion barrier layer are sequentially stacked along a direction away from the substrate. The light-emitting element includes an electrode and a conductive bump electrically connected to the electrode. The conductive bump has a second intermetallic layer, and the first diffusion barrier layer is located between the second intermetallic layer and the first intermetallic layer.

Abstract: Methods and systems are provided for an engine for adjusting cylinder parameter settings to optimize engine output during a transient mode. In one example, a method may include adjusting cylinder parameter settings, including a cam timing setting, a spark timing setting, and a fuel injection timing setting based on a chamber temperature in response to a rate of fuel injection acceleration being greater than a positive threshold, thus indicating the engine is in the transient mode.

Abstract: This application describes a thermal interface material, and preparation and application thereof. Specifically, a thermal interface material is described. The thermal interface material is obtained by bending and folding, optional horizontal pressing and optional high-temperature treatment of a laminated structure. Two-dimensional high-thermal-conductivity nano-plates on the upper surface and the lower surface of the thermal interface material have a horizontal stack structure. Two-dimensional high-thermal-conductivity nano-sheets located between the upper surface and the lower surface of the thermal interface material have both a vertical stack structure and a curved stack structure. Also described are a preparation method and application of the thermal interface material.

Abstract: Methods, electronic device, and non-transitory computer-readable storage mediums are provided for semantic parsing. The equipment may obtain a first recognition result of a target statement. The first recognition result may include a first intention recognition result and a first entity recognition result. The first entity recognition result may correspond to a plurality of vertical domains. The equipment may also determine one of the plurality of vertical domains corresponding to the first entity recognition result as a target vertical domain corresponding to the target statement according to the first intention recognition result. The equipment may further convert the first entity recognition result into a second entity recognition result in the target vertical domain. The equipment may also parse an intention of the target statement according to the second entity recognition result.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

Abstract: The invention provides a pixel unit, a pixel array, and a display panel. The pixel unit includes a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit, and the sub-pixel units share one data line. In the pixel unit of the present invention, which utilizes a plurality of sub-pixel units in the pixel unit sharing the same data line and simultaneously gate lines of a plurality of sub-pixel units arranging in parallel in the pixel unit, therefore, to save a wiring area, and an aperture ratio of the pixel unit is increased. Thereby increasing the light transmittance of the display panel and improving the display effect of the product.