Abstract: A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory has more bits and higher capacity than that of the memory with a single phase-change layer.

Abstract: A multilevel phase-change memory, manufacturing method and status transferring method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a series structure to form a memory cell. A current-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved by imposing different current levels. The provided multilevel phase-change memory has more bits and higher capacity than that of the memory with a single phase-change layer. Furthermore, the series structure may reduce the cell area and the device volume.

Abstract: A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.