Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.

Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: An EUV reflective structure includes a substrate and multiple pairs of a Si layer and a Mo layer. The Si layer includes a plurality of cavities.

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.

Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

Abstract: An apparatus for generating at least one particle shield. The at least one particle shield includes a first component and a second component. The first component and the second component are usable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of an object, the first particle shield is substantially parallel to and physically separated from the proximate surface of the object, and the first particle shield includes an energy gradient force or a velocity gradient force.

Abstract: The present disclosure provides an apparatus. The apparatus comprises a field generator, configured to produce a field shield protecting a reticle from foreign particles.

Abstract: An apparatus for generating at least one particle shield in photolithography includes a first component and a second component. The first component and the second component are operable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of an object. The first component includes a first gas injector, and the second component includes a first gas extractor corresponding to the first gas injector. The first gas injector is configured to blow out a gas, thereby forming the first particle shield. The first gas extractor is configured to work with the first gas injector for providing gas pressure gradient for the first particle shield.

Abstract: Methods and system for detecting hotspots in semiconductor wafer are provided. At least one semiconductor wafer is inspected to detect a plurality of hotspots of each die in the semiconductor wafer, wherein each of the hotspots has defect coordinates in a layout of the die. The hotspots of the dies are stacked in the layout according to the defect coordinates of the hotspots. A common pattern is obtained according to the stacked hotspots corresponding to a location with specific coordinates in the layout. It is determined whether the common pattern is a known pattern having an individual identification (ID) code. A new ID code is assigned to the common pattern when the common pattern is an unknown pattern.