Patents by Inventor Wen-Jeng Lin
Wen-Jeng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
-
Publication number: 20220373094Abstract: The present invention relates to a pressure resistance valve structure, which comprises a front valve seat body, a pressure resistance valve core body and a rear valve seat body. The pressure resistance valve core body is closed or released from the closed state relative to the front valve seat body, to control the export of liquid or gaseous fluids. The overall composition of the present invention is simple in structure, reducing the risk of component failure after long-term use, so as to achieve the effect of structural stability and good convenience of use.Type: ApplicationFiled: March 15, 2022Publication date: November 24, 2022Inventor: Wen-Jeng LIN
-
Patent number: 7638390Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: GrantFiled: September 7, 2007Date of Patent: December 29, 2009Assignee: United Microelectric Corp.Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Patent number: 7449741Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: GrantFiled: May 2, 2006Date of Patent: November 11, 2008Assignee: United Microeletronic Corp.Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Patent number: 7358556Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: GrantFiled: May 2, 2006Date of Patent: April 15, 2008Assignee: United Microelectronics Corp.Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Publication number: 20070298567Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: ApplicationFiled: September 7, 2007Publication date: December 27, 2007Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rem-Hurng Larn
-
Patent number: 7309890Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: GrantFiled: May 2, 2006Date of Patent: December 18, 2007Assignee: United Microelectronics Corp.Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Patent number: 7157763Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: GrantFiled: November 4, 2004Date of Patent: January 2, 2007Assignee: United Microelectronics Corp.Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Patent number: 7144777Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.Type: GrantFiled: February 25, 2005Date of Patent: December 5, 2006Assignee: United Microelectronics Corp.Inventors: Tzung-Han Lee, Wen-Jeng Lin, Kuang-Pi Lee, Blue Larn
-
Publication number: 20060202247Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: ApplicationFiled: May 2, 2006Publication date: September 14, 2006Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Publication number: 20060202248Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: ApplicationFiled: May 2, 2006Publication date: September 14, 2006Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Publication number: 20060197132Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: ApplicationFiled: May 2, 2006Publication date: September 7, 2006Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Publication number: 20060192241Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Inventors: Tzung-Han Lee, Wen-Jeng Lin, Kuang-Pi Lee, Blue Larn
-
Publication number: 20050156252Abstract: The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.Type: ApplicationFiled: December 15, 2004Publication date: July 21, 2005Inventors: Yung-Chang Lin, Le-Tien Jung, Wen-Jeng Lin
-
Publication number: 20050098905Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.Type: ApplicationFiled: November 4, 2004Publication date: May 12, 2005Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
-
Publication number: 20040166687Abstract: The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Inventors: Yung-Chang Lin, Le-Tien Jung, Wen-Jeng Lin
-
Patent number: 6689673Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.Type: GrantFiled: May 17, 2000Date of Patent: February 10, 2004Assignee: United Microelectronics Corp.Inventors: Kirk Hsu, Yuang-Chang Lin, Wen-Jeng Lin
-
Patent number: 6306760Abstract: The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, an array area and a periphery area. The array area comprises a first gate electrode and a second gate electrode adjacent to the first gate electrode. The periphery area comprises at least a third gate electrode. A first doped area is formed over each of two opposite sides of each gate electrode. A first spacer is formed on a wall of each of the two opposite sides of the third gate electrode in the periphery area. Then, a second spacer is formed on a wall of each of the two opposite sides of the first and second gate electrodes in the array area. The first spacers are thicker than the second spacers, and the second spacers between the first and second gate electrodes are internal walls of a self-aligned contact hole between the first and second gate electrodes.Type: GrantFiled: December 9, 1999Date of Patent: October 23, 2001Assignee: United Microelectronics Corp.Inventors: Hsin-Tuei Hsu, Yuang-Chang Lin, Wen-Jeng Lin
-
Patent number: 6281134Abstract: A method for forming combining a logic circuit and a capacitor of a passive element is disclosed. The method includes the following steps. First, a semiconductor wafer having a first dielectric layer and a first contact is provided. A first metal layer is formed on the first contact and around an estimated area. A second dielectric layer is formed on the first metal layer and the first dielectric layer. The second dielectric layer is formed on the first metal layer and the first dielectric layer. The second metal is formed on areas of the metal layer of the estimated areas. The third dielectric layer is formed on the second metal layer and the second dielectric layer. The fourth dielectric layer is formed on the third dielectric layer. The fifth dielectric layer is formed on the fourth dielectric layer. Sequentially the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, and the second dielectric layer are all etched.Type: GrantFiled: October 22, 1999Date of Patent: August 28, 2001Assignee: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Wen-Jeng Lin
-
Patent number: 6238958Abstract: A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer.Type: GrantFiled: December 31, 1999Date of Patent: May 29, 2001Assignee: United Microelectronics Corp.Inventors: Kirk Hsu, Yung-Chang Lin, Wen-Jeng Lin