Abstract: A camera module includes a lens assembly, a voice coil motor assembly, an image sensor assembly and a flash assembly. The lens assembly is installed in the voice coil motor assembly along an optical axis direction, the image sensor assembly is located below the lens assembly, the flash assembly is mounted above the voice coil motor assembly and includes at least one light source located around a lens of the lens assembly, and the light source adapted for providing a flash for the lens. The flash assembly can provide uniform and even flashing light for the lens to improve imaging quality, and provide compact structure to meet the development of the electronic products miniaturization.

Abstract: A camera module includes a lens assembly, a voice coil motor assembly for receiving and driving the lens assembly, and an image sensor assembly located below the voice coil motor assembly. The voice coil motor assembly comprises a bottom unit that is hollow and a color filter supported by the bottom unit, the color filter, the lens assembly and the image sensor assembly are coaxial, the bottom unit has an upper portion and a lower portion that are integrated together, the upper portion is configured around the lens assembly, and the bottom unit is configured below the lens assembly and supports the color filter. The camera module has simple structure and convenient assembly, can reduce total assembly tolerances of the camera module, achieve an accurate optical axis alignment between the lens and the image sensor, and reduce manufacturing cost to benefit the popularization in industries.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.

Abstract: A method for designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device.

Abstract: A method of determining colorability of a layout includes generating a conflict diagram based on circuit information. The conflict diagram includes a plurality of nodes, each node of the plurality of nodes is connected to at least another node of the plurality of nodes by a link, and each node of the plurality of nodes has a degree equal to a number of links connected to the node. The method includes setting a degree of each anchor node within the conflict diagram to a value of n, where n is equal to a number of mask usable to manufacture the layout. The method further includes excluding, using a processor, nodes having a degree less than n from the conflict diagram. The method further includes performing a color status check on the conflict diagram after the excluding; and determining whether the layout is colorable based on the performed color status check.

Abstract: A voice coil motor includes a housing having a cavity; a movable assembly received in the cavity; a fixing assembly configured outside of the movable assembly; and a first spring plate and a second spring plate configured at an upper surface and a lower surface of the movable assembly respectively. The fixing assembly comprises at least two magnetic elements connected with the first spring plate and a spacer member configured on the second spring plate to connect the second spring plate to the magnetic elements or the housing. The voice coil motor is served as an actuator of electronic products such as digital cameras, mobile phones, and digital cameras, which has thin thickness, good performance and strong applicability.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed for the layout. Using the localized mask loading and the global mask loading, if computed, a loading effect of a plurality of mask pattern schemes is evaluated to identify a mask pattern scheme having a desired loading effect.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: A method of determining colorability of a layout includes generating a conflict diagram based on circuit information. The conflict diagram includes a plurality of nodes, each node of the plurality of nodes is connected to at least another node of the plurality of nodes by a link, and each node of the plurality of nodes has a degree equal to a number of links connected to the node. The method includes setting a degree of each anchor node within the conflict diagram to a value of n, where n is equal to a number of mask usable to manufacture the layout. The method further includes excluding, using a processor, nodes having a degree less than n from the conflict diagram. The method further includes performing a color status check on the conflict diagram after the excluding; and determining whether the layout is colorable based on the performed color status check.

Abstract: Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (DRC) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.