Abstract: An independent graphics card system comprises an expansion motherboard, a system power supply, at least one expansion graphics card and a fan assembly. The system power supply is electrically connected to the expansion motherboard. The at least one expansion graphics card is plugged into the expansion motherboard through an adapter card. The at least one expansion graphics card is parallel with the expansion motherboard. The fan assembly dissipates heat of the at least one expansion graphics card.

Abstract: This application discloses a relay selection method and apparatus, a relay information transmission method and apparatus, and a terminal, and pertains to the technical field of communications. The method in the embodiments of this application includes: receiving, by a remote terminal, first information sent by a relay terminal, where the first information includes at least one of a relay hop count N or quality of service (QoS) information of the relay terminal, N represents an Nth hop of the relay terminal in a relay link, and N is a positive integer; and performing, by the remote terminal, relay terminal selection based on the first information.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.

Abstract: Disclosed herein is a light transmissive fiber integrated knit textile for use on consumer electronic products. The knit textile is depicted to be constructed with light transmissive fibers integration through a weave-in/inlay knit technique with a flat-bed knitting construction. The light transmissive knitted textile is also tethered to a portable electronic device, allowing for the light transmitting fibers knitted into the fabric to define a lighting display on said fabric.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.

Abstract: Disclosed herein is a flat-bed knit-based electrode structure that has non-electrically conductive regions and electrically conductive regions. The non-electrically conductive regions are formed from a knitted textile including non-conductive yarns, and the electrically conductive regions are formed from a knitted textile having electrically conductive yarn. The electrically conductive regions are knitted using a conductive hybrid yarn containing a non-conductive multifilament with polymer and coated with carbon. The electrically conductive regions can transmit electrical data or power signals along the knitted textile via the conductive yarn. A connector links the conductive region to a wireless device that can output heart rate data of the user.

Abstract: Disclosed herein is a light transmissive fiber integrated knit textile for use on consumer electronic products. The knit textile is depicted to be constructed with light transmissive fibers integration through a weave-in/inlay knit technique with a flat-bed knitting construction. The light transmissive knitted textile is also tethered to a portable electronic device, allowing for the light transmitting fibers knitted into the fabric to define a lighting display on said fabric.

Abstract: A method for fabricating a semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a barrier layer in the trench, forming a nucleation layer on the barrier layer, performing an anneal process to form a silicide layer, forming a bulk layer on the silicide layer, and forming a magnetic tunneling junction (MTJ) on the bulk layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

Abstract: A light source generating device, a projection apparatus and a light source generation method are provided. The light source generating device includes a first light source, an auxiliary light source, a control device, a driver and a current command generator. The first light source generates a first light beam. The auxiliary light source generates an auxiliary light beam corresponding to the first light beam. The control device generates a first driving signal to drive the first light source. The driver generates an auxiliary driving signal to drive the auxiliary light source according to the gate control signal and a current command. The current command generator receives an indication signal, and generates the current command according to the indication signal, wherein the indication signal corresponds to a driving current of the first light source. The invention has an effect of enhancing brightness/chrominance.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

Abstract: A semiconductor structure includes a substrate; a first inter-layer dielectric (ILD) layer on the substrate; an etch stop layer on the first ILD layer; a second inter-layer dielectric (ILD) layer on the etch stop layer; and a copper damascene interconnect layer disposed in the first ILD layer. A tungsten via structure is disposed in the second ILD layer and the etch stop layer, and is electrically connected to the copper damascene interconnect layer. The tungsten via structure includes a tungsten layer and a barrier layer surrounding the tungsten layer. An intermetallic layer is disposed between the barrier layer and the copper damascene interconnect layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: Embodiments include a method and apparatus for evaluating code in hierarchical architecture software, and a storage medium. The method includes acquiring layer definition information, of hierarchical architecture software to be tested, including layer information and intra-layer component information; scanning code of the hierarchical architecture software to be tested, to acquire basic information of the code including component information, intra-component file information and intra-file code metric information; mapping the basic information with the layer definition information, to obtain file information of each component in each layer of the hierarchical architecture software to be tested and intra-file code metric information; and calculating a code evaluation parameter of the hierarchical architecture software to be tested, based upon the file information of each component in each layer and the intra-file code metric information.

Abstract: A projection system, a beam generating apparatus, and a beam generating method are provided. The beam generating apparatus includes a plurality of light emitting devices, a plurality of drivers, and a first auxiliary driver. The light emitting devices respectively generate a plurality of color lights with different wavelengths. The drivers respectively drive the light emitting devices according to a plurality of control signals. The first auxiliary driver drives a first light emitting device according to a first auxiliary control signal, and adjusts brightness of the first light emitting device according to a first regulating signal. When the first auxiliary control signal is enabled, the control signal corresponding the first light emitting device is disabled.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

Abstract: Generating a wizard includes receiving a scheme as an input source to form a received scheme, wherein the received scheme is a taxonomy, receiving a defined set of content files to form received content files, and loading the received content files and the received scheme. The received content files can be tagged using the received scheme. A wizard can be generated using the received scheme. The generated wizard is capable of use with an application utilizing the scheme, wherein a change in the received scheme is directly represented in the generated wizard.

Abstract: A manufacturing method of a connection structure includes the following steps. A dielectric layer is formed on conductive structures. Openings are formed in the dielectric layer and expose the conductive structures. A tungsten nucleation layer is conformally formed on the dielectric layer and in the openings. A nitrogen-containing treatment is performed on the tungsten nucleation layer. A deposition process is performed to form a tungsten filling layer on the tungsten nucleation layer. An interfacial layer is formed between the tungsten nucleation layer and the tungsten filling layer by the deposition process. A fluorine concentration of the interfacial layer is higher than that of the tungsten filling layer. A chemical mechanical polishing (CMP) process is performed to remove a part of the tungsten nucleation layer and a part of the tungsten filling layer for forming connection structures. The interfacial layer is removed by the CMP process.