Patents by Inventor Wen-Kuo Li

Wen-Kuo Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7683427
    Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side beside the source region. A gate dielectric layer is formed between the gate and the semiconductor substrate, wherein the gate dielectric layer comprises two or more portions having different thicknesses arranged laterally in a way that the thicknesses of the portions gradually increase from one side beside the source doping region to the opposite side bordering the field oxide layer. With such structure, the hot carrier impact is minimized and the gate length can be scaled down to gain Idlin.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: March 23, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Lung Chen, Wen-Kuo Li
  • Publication number: 20090184368
    Abstract: An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 23, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Liu, Chin-Lung Chen, Ming-Tsung Tung, Wen-Kuo Li
  • Patent number: 7560774
    Abstract: An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: July 14, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Hung Liu, Chin-Lung Chen, Ming-Tsung Tung, Wen-Kuo Li
  • Publication number: 20090072308
    Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side beside the source region. A gate dielectric layer is formed between the gate and the semiconductor substrate, wherein the gate dielectric layer comprises two or more portions having different thicknesses arranged laterally in a way that the thicknesses of the portions gradually increase from one side beside the source doping region to the opposite side bordering the field oxide layer. With such structure, the hot carrier impact is minimized and the gate length can be scaled down to gain Idlin.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Chin-Lung Chen, Wen-Kuo Li