Patents by Inventor Wen Lee

Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186408
    Abstract: Transistors with improved saturation drain current and methods for making such transistors are disclosed. The gate is formed in the shape of a longitudinal trench and a plurality of lateral trenches below the longitudinal trench. The resulting dual-recess structure increases the surface area of the gate, which permits additional charge carriers and increases the saturation drain current of the transistor. Such transistors can be useful in high voltage and medium voltage applications such as in display driver integrated circuits.
    Type: Application
    Filed: January 5, 2023
    Publication date: June 6, 2024
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Ta-Yuan Kung, Chun-Hsun Lee, Chih-Wen Yao, Yi-Huan Chen, Ming-Ta Lei
  • Patent number: 12002854
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 12001109
    Abstract: The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate; and a conductive pattern. The conductive pattern is in electrical contact with the active layer, wherein the conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: June 4, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chung-Wen Yen, Yu-Tsung Liu, Chao-Hsiang Wang, Te-Yu Lee
  • Publication number: 20240170396
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
  • Patent number: 11987566
    Abstract: The present invention provides a novel compound for effectively preventing nerve damage and protecting nerves, and a preparation method thereof. Besides, the present invention also provides a pharmaceutical composition comprising the novel compound, and a use of the novel compound for preventing nerve damage and protecting nerves.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 21, 2024
    Assignee: GENHEALTH PHARMA CO., LTD.
    Inventors: Lain-Tze Lee, Hui-Ping Tsai, Yi-Wen Lin, Shu-Fen Huang, Shih-Hung Liu, Chin-Wei Liu, Pi-Tsan Huang, Mei-Hui Chen
  • Publication number: 20240164099
    Abstract: An integrated circuit structure includes a substrate, semiconductor devices, an inter-layer dielectric (ILD) structure, an interconnect, a dielectric layer, an etching barrier layer, a conductive layer, and memory units. The semiconductor devices are on the substrate. The ILD structure is over the semiconductor devices. The interconnect is in the ILD structure and electrically connected to the semiconductor devices. The dielectric layer is over the ILD structure. The etching barrier layer is on the first dielectric layer. The conductive layer is on the etching barrier layer. The memory units are stacked in a vertical direction over the etching barrier layer.
    Type: Application
    Filed: March 15, 2023
    Publication date: May 16, 2024
    Inventors: Hong-Ji LEE, Tzung-Ting HAN, Chang-Wen JIAN
  • Patent number: 11984331
    Abstract: The present disclosure relates to an equipment front end module (EFEM) teaching element. The EFEM teaching element includes a memory element configured to store data describing an initial position of an EFEM robot within an EFEM chamber. A position measurement device is configured to take measurements describing a new position of the EFEM robot within the EFEM chamber that is different than the initial position of the EFEM robot. A controller is configured to determine a set of new movement commands describing a path of the EFEM robot based upon the data describing the initial position of the EFEM robot and the measurements.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240150473
    Abstract: The present disclosure provides engineered WNT agonists and methods of treating gastrointestinal disorders with modulators of the WNT signaling pathway.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 9, 2024
    Inventors: Russell FLETCHER, Sungjin LEE, Yang LI, Chenggang LU, Parthasarathy SAMPATHKUMAR, Geertrui VANHOVE, Wen-Chen YEH, Liqin XIE, Leonard PRESTA
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Patent number: 11978496
    Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Patent number: 11978751
    Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wen Huang, Chung-Liang Cheng, Ping-Hao Lin, Kuo-Cheng Lee
  • Publication number: 20240145380
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
  • Publication number: 20240147220
    Abstract: A capability reporting method and a modem chip performing the same are provided. The capability reporting method includes the following steps. A capability enquiry message is received from a network. A plurality of weightings for a serving Radio Access Technology (RAT) and at least one non-serving RAT are determined. The weighting for the at least one non-serving RAT is downgraded. A plurality of capability information for the serving RAT and the non-serving RAT are composed according to the weightings. The size of the capability information for the at least one non-serving RAT is reduced. The capability information for the serving RAT and the capability information for the at least one non-serving RAT are combined to obtain a capability report message. The capability report message is replied to the network.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 2, 2024
    Inventors: Lung-Wen CHEN, Tsung-Ming LEE
  • Publication number: 20240144728
    Abstract: Methods and systems are presented for signed document image analysis and fraud detection. An image of a document may be received from a user's device. A first layer of a machine learning engine is used to identify a signature and a name of the user within different areas of the received image. A second layer of the machine learning engine is used to extract a plurality of features from the different areas of the image. The plurality of features includes at least one visual feature representing the signature and at least one textual feature representing the name. A combined feature representation of the signature and the name is generated based on the plurality of features extracted from the image. A third layer of the machine learning engine is used to determine whether the signature of the user has been digitally altered, based on the combined feature representation.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: Quan Jin Ferdinand Tang, Jiyi Zhang, Jiazheng Zhang, Shanshan Peng, Jia Wen Lee
  • Publication number: 20240147825
    Abstract: Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Chung-chia CHEN, Yu-Hsin LIN, Ji Young CHOUNG, Jungmin LEE, Wen-Hao WU, Dieter HAAS
  • Patent number: 11972975
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Patent number: 11973501
    Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 30, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Publication number: 20240135745
    Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: InnnoLux Corporation
    Inventors: Kuei-Sheng Chang, Po-Yang Chen, Kuo-Jung Wu, I-An Yao, Wei-Cheng Lee, Hsien-Wen Huang
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee