Patents by Inventor Wen Ling

Wen Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240364696
    Abstract: An example operation may include one or more of storing access requirements of a containerized environment, identifying a plurality of types of users of the containerized environment based on the access requirements, identifying a plurality of different restriction priorities for the plurality of types of users within the containerized environment, respectively, based on the access requirements, dynamically generating an access policy that satisfies the plurality of different restriction priorities for the plurality of types of users within the containerized environment, and transforming the access policy into a plugin.
    Type: Application
    Filed: April 29, 2023
    Publication date: October 31, 2024
    Inventors: YAN HUANG, Zheng Lei An, Lei Wang, Shuang Shuang Jia, Heng Wang, Xiao Ling Chen, Wen Ya Zhou, Qing Yu Pei
  • Patent number: 12129418
    Abstract: The present invention relates to compositions and methods for selectively etching silicon nitride in the presence of silicon oxide, polysilicon and/or metal silicides at a high etch rate and with high selectivity. Additives are described that can be used at various dissolved silica loading windows to provide and maintain the high selective etch rate and selectivity.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 29, 2024
    Assignee: ENTEGRIS, INC.
    Inventors: Hsing-Chen Wu, Min-Chieh Yang, Ming-Chi Liao, Wen Hua Tai, Wei-Ling Lan
  • Patent number: 12130548
    Abstract: A reticle is provided. The reticle includes a first reflective multilayer (ML) over a mask substrate and a capping layer over the first reflective ML. The reticle also includes a first absorption layer over the capping layer and a second reflective multilayer (ML) over the first absorption layer. The reticle further includes an etch stop layer over the second reflective ML and a third reflective multilayer (ML) over the etch stop layer. In addition, the reticle includes an absorption film pair over the third reflective ML.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang Hsueh, Huan-Ling Lee, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 12132634
    Abstract: A method may include receiving current environment condition information associated with an extended reality device; receiving historical environment condition information associated with the extended reality device; based on current environment condition information and the historical environment condition information, determining one or more adjustments to meet a performance threshold for rendering objects on the an extended reality device or using the an extended reality device; and sending instructions to implement the one or more adjustments to meet the performance threshold for rendering objects on the extended reality device or using the extended reality device.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: October 29, 2024
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Eric Zavesky, Wen-Ling Hsu, Tan Xu
  • Publication number: 20240355393
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Patent number: 12122123
    Abstract: A composite material structure, including an outer layer, an inner layer, and a middle layer, is provided. The outer layer includes a metallic material. The inner layer includes a fiber material and a resin material. The outer layer has a first thickness, the inner layer has a second thickness, and the first thickness is different from the second thickness. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. Two opposite surfaces of the middle layer are respectively in direct contact with the outer layer and the inner layer. A manufacturing method of the composite material structure is also provided.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: October 22, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Ching Huang, Sheng-Hung Lee, Jung-Chin Wu, Kuo-Nan Ling, Chih-Wen Chiang, Chien-Chu Chen
  • Publication number: 20240347506
    Abstract: The disclosure provides a method of forming a package structure, and the method includes the following steps. A plurality of semiconductor components is bonded to a substrate. A grinding process is performed to thin the plurality of semiconductor components. The plurality of semiconductor components have a first total thickness variation (TTV) after performing the grinding process. A dielectric layer is formed on the substrate. A first chemical mechanical polishing (CMP) is performed to remove a first portion of the dielectric layer on top surfaces of the plurality of semiconductor components; and performing a second CMP process to remove a second portion of the dielectric layer between the plurality of semiconductor components and a portion of the plurality of semiconductor components. After performing the second CMP process, the plurality of semiconductor components has a second TTV less than the first TTV.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Patent number: 12101931
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12082171
    Abstract: Certain aspects of the present disclosure provide techniques for indicating capability of a user equipment (UE) to support multiple sounding reference signals (SRSs) with a single subframe, with at least one of frequency hopping, different bandwidths, or antenna switching for the multiple SRSs in the same subframe.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: September 3, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Alberto Rico Alvarino, Le Liu, Peter Gaal, Supratik Bhattacharjee, Qiang Shen, Rebecca Wen-ling Yuan
  • Publication number: 20240289017
    Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 29, 2024
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Dong Dong Yao, Yun Peng Zhang, Kuai Cao, En Yang Wang, Wen Qing Lv
  • Publication number: 20240292098
    Abstract: The invention provides an electronic device and a gain calibration method for an image stabilization function thereof. The method includes the following. The image stabilization function is activated. A first image is generated by using a first gain through an image capturing device, and a first blur degree of the first image is obtained. A second image is generated by using a second gain through the image capturing device, and a second blur degree of the second image is obtained. A reference blur degree corresponding to the second gain is determined according to the second blur degree. A calibrated gain for the image stabilization function is determined according to a linear relationship established between the first blur degree corresponding to the first gain and the reference blur degree corresponding to the second gain.
    Type: Application
    Filed: September 15, 2023
    Publication date: August 29, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Jo-Fan Wu, Wen-Ling Lin
  • Publication number: 20240284521
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node via a source cell, a medium access control (MAC) control element (MAC-CE) triggering a handover from the source cell to a target cell in an activated cell set configured for Layer 1/Layer 2 (L1/L2) mobility. The UE may transmit, to the network node via the target cell, a physical random access channel (PRACH) to initiate an aperiodic contention-free random access (CFRA) procedure in the target cell in a random access channel (RACH) occasion in a PRACH slot associated with a slot offset indication received from the network node. Numerous other aspects are described.
    Type: Application
    Filed: February 15, 2024
    Publication date: August 22, 2024
    Inventors: Jae Ho RYU, Yan ZHOU, Rebecca Wen-Ling YUAN, Changhwan PARK
  • Publication number: 20240282637
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Application
    Filed: March 22, 2024
    Publication date: August 22, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20240282628
    Abstract: A method of forming a semiconductor structure includes forming a seed layer on a substrate, forming a photoresist layer on the seed layer with a first opening wider than a second opening, performing an electroplating process with a first plating current to grow a bottom portion of a first metal line in the first opening and a bottom portion of a second metal line in the second opening, continuing the electroplating process with a second plating current that is larger than the first plating current to grow a top portion of the first metal line and a top portion of the second metal line, removing the photoresist layer to expose a portion of the seed layer, and removing the exposed portion of the seed layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: August 22, 2024
    Inventors: Dian-Hau CHEN, Chen-Chiu HUANG, Hsiang-Ku SHEN, ShuFang CHEN, Ying-Yao LAI, Wen-Ling CHANG, Chi-Feng LIN, Peng-Chung JANGJIAN, Jo-Lin LAN, Fang-I Chih
  • Patent number: 12068032
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Patent number: 12055655
    Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals is provided. In particular, the disclosure provides an intrusion detection system adapted to receive radar signals and distinguish a potential ghost target from a legitimate target based on a signal to noise ratio of the radar signals and a range to the ghost target and the legitimate target.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Qian Wang, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Vuk Lesi, Manoj Sastry, Ivan Simoes Gaspar
  • Patent number: 12051672
    Abstract: The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Patent number: 12048164
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin