Patents by Inventor Wen Ma
Wen Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170226574Abstract: A nucleic acid isothermal amplification method is based on a polymerase spiral reaction using only one pair of primers. The method employs a self-spiraling amplification method, and has a high amplification efficiency.Type: ApplicationFiled: July 7, 2015Publication date: August 10, 2017Inventors: Liuyu HUANG, Wei LIU, Derong DONG, Zeliang CHEN, Dayang ZOU, Zhan YANG, Simo HUANG, Ningwei LIU, Yaqing XU, Yue TANG, Wen MA
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Patent number: 9674012Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.Type: GrantFiled: February 8, 2016Date of Patent: June 6, 2017Assignee: MStar Semiconductor, Inc.Inventors: Ching-Wen Ma, Tai-Lai Tung
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Publication number: 20170104614Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.Type: ApplicationFiled: February 8, 2016Publication date: April 13, 2017Inventors: Ching-Wen MA, Tai-Lai TUNG
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Patent number: 9503292Abstract: A method for calculating a feed forward equalizer coefficient of a feed forward equalizer in a minimum mean square error decision feedback equalizer (MMSE-DFE) based on a fast transversal recursive least squares (FT-RLS) algorithm is provided. The length of the feed-forward equalizer is LF, which is a positive integer. The method includes an outer iteration having an LF number of iterations. The outer iteration includes an inner iteration having an n number of iterations, where n is an integer between 0 and (LF?2).Type: GrantFiled: October 28, 2015Date of Patent: November 22, 2016Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Ching-Wen Ma, Chih-Cheng Kuo, Tai-Lai Tung, Chih-Ching Chen
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Publication number: 20160119136Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an indecipherable signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the indecipherable signal to generate an encrypted message.Type: ApplicationFiled: May 15, 2014Publication date: April 28, 2016Applicant: MStar Semiconductor, Inc.Inventor: Ching-Wen Ma
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Patent number: 8796066Abstract: Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remain to serve as the back contact of the cell.Type: GrantFiled: August 24, 2010Date of Patent: August 5, 2014Assignee: Sunpreme, Inc.Inventors: Ashok Sinha, Wen Ma
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Patent number: 8254221Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.Type: GrantFiled: January 24, 2012Date of Patent: August 28, 2012Assignee: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Yung-Chi Yang
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Publication number: 20120120782Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Inventors: Ching-Wen Ma, Yung-Chi Yang
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Patent number: 8134895Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.Type: GrantFiled: June 13, 2008Date of Patent: March 13, 2012Assignee: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Yung-Chi Yang
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Patent number: 8112052Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.Type: GrantFiled: July 14, 2010Date of Patent: February 7, 2012Assignee: Sunplus Technology Co., Ltd.Inventor: Ching-Wen Ma
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Patent number: 8055981Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.Type: GrantFiled: November 9, 2007Date of Patent: November 8, 2011Assignee: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Zheng-Xiong Chen, Shih-Hsien Liu
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Publication number: 20110018630Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.Type: ApplicationFiled: July 14, 2010Publication date: January 27, 2011Applicant: Sunplus Technology Co., Ltd.Inventor: Ching-Wen Ma
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Publication number: 20100317146Abstract: Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remain to serve as the back contact of the cell.Type: ApplicationFiled: August 24, 2010Publication date: December 16, 2010Applicant: SUNPREME, LTD.Inventors: Ashok Sinha, Wen Ma
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Patent number: 7805662Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.Type: GrantFiled: February 9, 2007Date of Patent: September 28, 2010Assignee: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Kuo-Ming Wang, Jia-Ping Chen
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Publication number: 20090206056Abstract: A multi-station workpiece processing system provides a targeted equal share of a regulated input process gas flow to each active processing station of a plurality of active processing stations using a single gas flow regulator for each gas and irrespective of the number of inactive processing stations.Type: ApplicationFiled: February 6, 2009Publication date: August 20, 2009Inventors: Songlin Xu, Daniel J. Devine, Wen Ma, Ce Qin, Vijay Vaniapura
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Publication number: 20090069926Abstract: CNC apparatus having a mechanism for controlling length variation of a lead screw due to thermal expansion and method therefore when the apparatus is rotating in high speed and/or when load is high are disclosed. The lead screw is supported by two spaced ball bearing sets and is hollow to permit cooling fluid to flow through. A deflection detecting unit is disposed proximate one ball bearing set for detecting its deflection. In one embodiment, an adjusting nut is operatively connected to one end of the lead screw and is adapted to pre-stress the ball bearing set. The method includes pre-stressing the ball bearing set for deflecting in one direction and in operation in response to detecting the ball bearing set deflected in an opposite direction cooling the lead screw for substantially maintaining its length unchanged with respect to a bed.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventor: Tsu-Wen Ma
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Publication number: 20080310273Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.Type: ApplicationFiled: June 13, 2008Publication date: December 18, 2008Inventors: Ching-Wen MA, Yung-Chi YANG
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Publication number: 20080115018Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.Type: ApplicationFiled: November 9, 2007Publication date: May 15, 2008Inventors: Ching-Wen Ma, Zheng-Xiong Chen, Shih-Hsien Liu
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Publication number: 20070204207Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.Type: ApplicationFiled: February 9, 2007Publication date: August 30, 2007Applicant: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Kuo-Ming Wang, Jia-Ping Chen
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Patent number: 7187739Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.Type: GrantFiled: May 16, 2003Date of Patent: March 6, 2007Assignee: Via Technologies, Inc.Inventor: Ching-Wen Ma