Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) epitaxial feature disposed over a substrate, a second S/D epitaxial feature adjacent the first S/D epitaxial feature, and a hybrid fin disposed between the first and second S/D epitaxial features. The hybrid fin includes a first dielectric material, a second dielectric material disposed on the first dielectric material, a dielectric layer surrounding the first and second dielectric materials, and a high-k dielectric layer disposed in the first and second dielectric materials. The high-k dielectric layer has an upper surface located at a level between a level of an upper surface of the second dielectric material and a level of a lower surface of the second dielectric material.

Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: A semiconductor wafer packaging system to cushion semiconductor wafers from damage from shock and vibration during transportation is described. The semiconductor wafer packaging system has at least one a wafer case to enclose the semiconductor wafers. Each wafer case is placed within a wafer case padding unit. Each padding unit includes a rectangular cushioning block and a plurality of trapezoidal spacer blocks affixed to the four sides of the rectangular cushioning block. The rectangular cushioning block has an opening to accept the wafer case and a plurality of trapezoidal notches on two adjoining sides of the rectangular cushioning block. The wafer case padding unit is placed within a packaging canister for transportation.

Abstract: An improved container for storing large diameter semiconductor wafers. The container has a body member and an enclosure member that are secured together with complimentary threaded portions. The top of the enclosure member has a circular upstanding flange spaced from a circular upstanding protrusion. Upstanding radially ribs are provided between the flange and protrusion to strengthen the enclosure member and provide a means for engagement with a wrench that will apply a torque force.

Abstract: A cushioned holder for a cylindrical container for a semiconductor wafer is formed of a stack of layers of a cushioning material that each have a rectangular opening for receiving the container; the layers are spaced from the box by several absorbers having a mirrored pyramidal frustum shape. The shape is easy to manufacture and it provides improved cushioning without increasing the space occupied by the layers.