Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.

Abstract: The present invention provides a solar cell with a surface staged type antireflective layer, comprising a photoelectric conversion layer having a first surface and a second surface opposite from each other and used for receiving incident photons in order to generate charged carriers; a staged type antireflective layer formed on the first surface; the staged type antireflective layer comprising a textured surface structure formed on the first surface via a coarsening method and a plurality of nanostructures formed to protrude from or indent into the textured surface structure; a front-side conductive layer disposed on top the staged type antireflective layer; and a back-side conductive layer disposed underneath the second surface; wherein the s staged type antireflective layer is used for allowing the solar cell to generate an antireflection effect subject to light in a full spectrum range; wherein the full spectrum range is between 300 nm to 1100 nm.

Abstract: A method for manufacturing a semiconductor template balanced between strains and defects is provided, the method including steps of: preparing a substrate, dividing the substrate into a plurality of first patterned zones and a plurality of second patterned zones, the second patterned zones applied to separate the first patterned zones; selecting a semiconductor with an ideal lattice of a semiconductor buffer layer to be deposited on the substrate; etching a plurality of first microstructures in the first patterned zones according to the semiconductor with the ideal lattice, the first microstructures and the semiconductor with the ideal lattice following a lattice-structure matching relationship, discovered by strain-traction experiments, making the substrate a multi-patterned substrate; and depositing the semiconductor buffer layer having the semiconductor with the ideal lattice on the multi-patterned substrate to manufacture a semiconductor template which is balanced between strains and defects.

Abstract: A method for manufacturing a semiconductor template balanced between strains and defects is provided, the method including steps of: preparing a substrate, dividing the substrate into a plurality of first patterned zones and a plurality of second patterned zones, the second patterned zones applied to separate the first patterned zones; selecting a semiconductor with an ideal lattice of a semiconductor buffer layer to be deposited on the substrate; etching a plurality of first microstructures in the first patterned zones according to the semiconductor with the ideal lattice, the first microstructures and the semiconductor with the ideal lattice following a lattice-structure matching relationship, discovered by strain-traction experiments, making the substrate a multi-patterned substrate; and depositing the semiconductor buffer layer having the semiconductor with the ideal lattice on the multi-patterned substrate to manufacture a semiconductor template which is balanced between strains and defects.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated-package products.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated-package products.