Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a reactivity reducing coating over one or more lower interconnect layers disposed over a substrate. A bottom electrode layer is formed on and in contact with the reactivity reducing coating. The bottom electrode layer has a first electronegativity that is less than or equal to a second electronegativity of the reactivity reducing coating. A data storage element is formed over the bottom electrode layer and a top electrode layer is formed over the data storage element. The top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer are patterned to define a memory device.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

Abstract: The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.