Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.

Abstract: Disclosed is a test tape device comprising a housing having a cassette compartment for a replaceable tape cassette, a cassette door which can be retained in a closed position and which allows access to the cassette compartment through a housing opening in an open position, a tip cover which can be positioned in a first position covering a housing aperture and a second position allowing access to a tip of the tape cassette, wherein the tip cover is moveable to a third position in which the cassette tip is at least partially uncovered and the housing opening is extended into the area of the cassette tip, and wherein the cassette door is self-opening when moving the tip cover to the third position.

Abstract: Disclosed is a test tape device comprising a housing having a cassette compartment for a replaceable tape cassette, a cassette door which can be retained in a closed position and which allows access to the cassette compartment through a housing opening in an open position, a tip cover which can be positioned in a first position covering a housing aperture and a second position allowing access to a tip of the tape cassette, wherein the tip cover is moveable to a third position in which the cassette tip is at least partially uncovered and the housing opening is extended into the area of the cassette tip, and wherein the cassette door is self-opening when moving the tip cover to the third position.

Abstract: A test tape device is disclosed herein for use with a replaceable analytical tape cassette, where the device includes a housing having a cassette compartment covered by a cassette door and a housing opening for sample application, a protective cover that can be moved between a closed position covering the housing opening and a release position allowing access to the housing opening and a door lock for retaining the cassette door in the closed position, wherein the protective cover is coupled with the door lock via an interlocking mechanism, such that the door lock can only be unlocked in the release position of the cover.

Abstract: A test tape device is disclosed herein for use with a replaceable analytical tape cassette, where the device includes a housing having a cassette compartment covered by a cassette door and a housing opening for sample application, a protective cover that can be moved between a closed position covering the housing opening and a release position allowing access to the housing opening and a door lock for retaining the cassette door in the closed position, wherein the protective cover is coupled with the door lock via an interlocking mechanism, such that the door lock can only be unlocked in the release position of the cover.

Abstract: A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor.

Abstract: A touch panel fabrication method includes the steps of (a) preparing a first substrate and a second substrate, (b) disposing a seal frame having an opening on the first substrate, (c) coupling the first substrate and the second substrate together by the seal frame such that a vacancy is defined by the first substrate, the second substrate and the seal frame, and (d) filling up the vacancy with a dielectric material through the opening of the seal frame.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

Abstract: A contact of an electrical connector includes an upper section for engaging a pin of a central processing unit module, a lower section retained in a bore defined in a housing of the connector with a tail section extending therefrom for being electrically connected to a circuit board and a plurality of spaced connecting sections, serving as signal transmission channels, arranged between the upper and lower sections and electrically connected thereto to serve as electrical current channels. By increasing the number of the connecting sections, the total cross-sectional area of the electrical channels is increased which effectively reduces the inductance thereof.