Patents by Inventor Wen-Wei Shen

Wen-Wei Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8241963
    Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Yao-Chun Chuang, Chen-Shien Chen, Ming-Fa Chen
  • Patent number: 8202800
    Abstract: A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: June 19, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Chen-Cheng Kuo, Wen-Wei Shen
  • Patent number: 8178970
    Abstract: A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: May 15, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen, Ching-Wen Hsiao
  • Publication number: 20120012997
    Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Yao-Chun Chuang, Chen-Shien Chen, Ming-Fa Chen
  • Publication number: 20110291262
    Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Chen-Shien Chen, Chen-Cheng Kuo, Ming-Fa Chen, Rung-De Wang
  • Publication number: 20110285023
    Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 24, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Ying-Ching Shih, Chen-Shien Chen, Ming-Fa Chen
  • Publication number: 20110217841
    Abstract: A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 8, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hua CHEN, Chen-Shien CHEN, Chen-Cheng KUO, Wen-Wei SHEN
  • Patent number: 7969013
    Abstract: A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Chen-Cheng Kuo, Wen-Wei Shen
  • Publication number: 20110095436
    Abstract: A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad.
    Type: Application
    Filed: June 2, 2010
    Publication date: April 28, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hua CHEN, Chen-Shien CHEN, Chen-Cheng KUO, Wen-Wei SHEN
  • Publication number: 20110068465
    Abstract: A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 24, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Wei Shen, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen, Ching-Wen Hsiao
  • Publication number: 20100084747
    Abstract: A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad.
    Type: Application
    Filed: October 3, 2008
    Publication date: April 8, 2010
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Chen-Cheng Kuo, Wen-Wei Shen